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1. general description the p89lpc933/934/935/936 is a single-chip microcontroller, available in low cost packages, based on a high performance processo r architecture that ex ecutes instructions in two to four clocks, six times the rate of standard 80c51 devices. many system-level functions have been incorporated into the p89lpc933/934/935/936 in order to reduce component count, board space, and system cost. 2. features and benefits 2.1 principal features ? 4 kb/8 kb/16 kb byte-erasable flash code me mory organized into 1 kb/2 kb sectors and 64-byte pages. single-byte erasing allows any byte(s) to be used as non-volatile data storage. ? 256-byte ram data memory. both the p89lpc935 and p89lpc936 also include a 512-byte auxiliary on-chip ram. ? 512-byte customer da ta eeprom on chip allows seria lization of devices, storage of setup parameters, et c. (p89lpc935/936). ? dual 4-input multiplexed 8-bit a/d conver ters/dac outputs (p89lpc935/936, single a/d on p89lpc933/934).two analog comparators with selectable inputs and reference source. ? two 16-bit counter/timers (each may be conf igured to toggle a port output upon timer overflow or to become a pwm output) and a 23 -bit system timer that can also be used as an rtc. ? enhanced uart with fractional baud rate generator, break detect, framing error detection, and automatic address detection; 400 khz byte-wide i 2 c-bus communication port and spi communication port. ? capture/compar e unit (ccu) provides pwm, input capture, and output compare functions (p89lpc935/936). ? high-accuracy intern al rc oscillator option allows oper ation without external oscillator components. the rc oscilla tor option is selectab le and fine tunable. ? 2.4 v to 3.6 v v dd operating range. i/o pins are 5 v tolerant (may be pulled up or driven to 5.5 v). ? 28-pin tssop, plcc, and hvqfn packages with 23 i/o pins minimum and up to 26 i/o pins while using on-chip oscillator and reset options. p89lpc933/934/935/936 8-bit microcontroller with accel erated two-clock 80c51 core 4 kb/8 kb/16 kb 3 v byte-e rasable flash with 8-bit adcs rev. 8 ? 12 january 2011 product data sheet
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 2 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 2.2 additional features ? a high performance 80c51 cpu provides inst ruction cycle times of 111 ns to 222 ns for all instructions except multiply and divi de when executing at 18 mhz. this is six times the performance of the standard 80c5 1 running at the same clock frequency. a lower clock frequency for the same performance results in power savings and reduced emi. ? serial flash in-circuit programming (icp ) allows simple production coding with commercial eprom programmers. flash security bits prevent reading of sensitive application programs. ? serial flash in-system programming (isp) a llows coding while the device is mounted in the end application. ? in-application programming (iap) of the flash code memory. this allows changing the code in a running application. ? watchdog timer with separate on-chip oscilla tor, requiring no ex ternal components. the watchdog prescaler is selectable from eight values. ? low voltage reset (brownout detect) allows a graceful system shutdown when power fails. may optionally be configured as an interrupt. ? idle and two different power-down reduced power modes. improved wake-up from power-down mode (a low interrupt input starts execution). typical power-down current is 1 a (total power-down with voltage comparators disabled). ? active-low reset. on-chip power-on reset allows operation without external reset components. a reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. a software reset function is also available. ? configurable on-chip oscilla tor with frequency range op tions selected by user programmed flash configurat ion bits. oscillator options support frequencies from 20 khz to the maximum operating frequency of 18 mhz. ? oscillator fail detect. the watchdog timer has a separate fully on-chip oscillator allowing it to perform an os cillator fail detect function. ? programmable port output configuration opti ons: quasi-bidirectional, open drain, push-pull, input-only. ? port ?input pattern match? detect. port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. ? led drive capability (20 ma) on all port pi ns. a maximum limit is specified for the entire chip. ? controlled slew rate port outputs to reduce emi. outputs have approximately 10 ns minimum ramp times. ? only power and ground connections are required to operate the p89lpc933/934/935/936 when internal reset option is selected. ? four interrupt pr iority levels. ? eight keypad interrupt inputs, plus two additional external interrupt inputs. ? schmitt trigger port inputs. ? second data pointer. ? emulation support.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 3 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 3. product comparison overview ta b l e 1 highlights the differences between the four devices. for a complete list of device features please see section 2 ? features and benefits ? . 4. ordering information 4.1 ordering options table 1. product comparison overview device flash memory sector size adc1 adc0 ccu data eeprom p89lpc933 4 kb 1 kb x - - - p89lpc934 8 kb 1 kb x - - - p89lpc935 8 kb 1 kb x x x x p89lpc936 16 kb 2 kb x x x x table 2. ordering information type number package name description version p89lpc935fa plcc28 plastic leaded chip carrier; 28 leads sot261-2 p89lpc933hdh tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 p89lpc933fdh p89lpc934fdh p89lpc935fdh P89LPC936FDH p89lpc935fhn hvqfn28 plastic thermal enhanced very thin quad flat package; no leads; 28 terminals; body 6 6 0.85 mm sot788-1 table 3. ordering options type number flash memory temperature range frequency p89lpc933hdh 4 kb ? 40 cto+125 c 0 mhzto18mhz p89lpc933fdh 4 kb ? 40 cto+85 c p89lpc935fa 8 kb p89lpc934fdh p89lpc935fdh p89lpc935fhn P89LPC936FDH 16 kb
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 4 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 5. block diagram fig 1. block diagram accelerated 2-clock 80c51 cpu 4 kb/8 kb/16 kb code flash 256-byte data ram port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os keypad interrupt programmable oscillator divider cpu clock configurable oscillator on-chip rc oscillator internal bus crystal or resonator power monitor (power-on reset, brownout reset) 002aab070 uart analog comparators 512-byte auxiliary ram i 2 c-bus 512-byte data eeprom (p89lpc935/936) port 3 configurable i/os ccu (capture/ compare unit) (p89lpc935/936) p89lpc933/934/935/936 watchdog timer and oscillator timer 0 timer 1 real-time clock/ system timer spi adc1/dac1 adc0/dac0 (p89lpc935/936) p3[1:0] p2[7:0] p1[7:0] p0[7:0] x2 x1 txd rxd scl sda t0 t1 cmp2 cin2b cin2a cmp1 cin1a cin1b oca ocb occ ocd ica ad10 ad11 ad12 ad13 dac1 ad00 ad01 ad02 ad03 dac1 icb spiclk mosi miso ss
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 5 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 6. pinning information 6.1 pinning fig 2. p89lpc933/934 tssop28 pin configuration fig 3. p89lpc935/936 tssop28 pin configuration p89lpc933hdh p89lpc933fdh p89lpc934fdh 002aab071 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 p2.7 p2.6 p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p0.3/cin1b/kbi3/ad12 p0.4/cin1a/kbi4/dac1/ad13 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd p2.5/spiclk p2.4/ss p2.0/dac0 p2.1 p0.0/cmp2/kbi0 p1.7 p1.6 p1.5/rst v ss p3.1/xtal1 p3.0/xtal2/clkout p1.4/int1 p1.3/int0/sda p1.2/t0/scl p2.2/mosi p2.3/miso p89lpc935fdh P89LPC936FDH 002aab072 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 p2.0/icb/dac0/ad03 p2.1/ocd/ad02 p0.0/cmp2/kbi0/ad01 p1.7/occ/ad00 p1.6/ocb p1.5/rst v ss p3.1/xtal1 p3.0/xtal2/clkout p1.4/int1 p1.3/int0/sda p1.2/t0/scl p2.2/mosi p2.3/miso p2.7/ica p2.6/oca p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p0.3/cin1b/kbi3/ad12 p0.4/cin1a/kbi4/dac1/ad13 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.0/txd p1.1/rxd p2.5/spiclk p2.4/ss
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 6 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 4. p89lpc935 plcc28 pin configuration fig 5. p89lpc935 hvqfn28 pin configuration p89lpc935fa 002aab074 5 6 7 8 9 10 11 25 24 23 22 21 20 19 12 13 14 15 16 17 18 4 3 2 1 28 27 26 p1.6/ocb p1.5/rst v ss p3.1/xtal1 p3.0/xtal2/clkout p1.4/int1 p1.3/int0/sda p1.7/occ/ad00 p0.0/cmp2/kbi0/ad01 p2.1/ocd/ad02 p2.0/icb/dac0/ad03 p2.7/ica p2.6/oca p0.1/cin2b/kbi1/ad10 p0.2/cin2a/kbi2/ad11 p0.3/cin1b/kbi3/ad12 p0.4/cin1a/kbi4/dac1/ad13 p0.5/cmpref/kbi5 v dd p0.6/cmp1/kbi6 p0.7/t1/kbi7 p1.2/t0/scl p2.2/mosi p2.3/miso p2.4/ss p2.5/spiclk p1.1/rxd p1.0/txd 002aab076 p89lpc935fhn transparent top view 7 15 6 16 5 17 4 18 3 19 2 20 1 21 8 9 10 11 12 13 14 28 27 26 25 24 23 22 terminal 1 index area p1.7/occ/ad00 p2.7/ica p2.1/ocd/ad02 p2.0/icb/dac0/ad03 p0.0/cmp2/kbi0/ad01 p2.6/oca p0.1/cin2b/kbi1/ad10 p2.4/ss p2.2/mosi p2.3/miso p1.2/t0/scl p2.5/spiclk p1.0/txd p1.1/rxd p1.4/int1 p1.3/int0/sda p3.0/xtal2/clkout p3.1/xtal1 v ss p1.5/rst p1.6/ocb p0.6/cmp1/kbi6 p0.7/t1/kbi7 p0.5/cmpref/kbi5 v dd p0.4/cin1a/kbi4/dac1/ad13 p0.3/cin1b/kbi3/ad12 p0.2/cin2a/kbi2/ad11
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 7 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 6.2 pin description table 4. pin description symbol pin type description tssop28, plcc28 hvqfn28 p0.0 to p0.7 i/o port 0: port 0 is an 8-bit i/o port wit h a user-configurable output type. during reset port 0 latches are configured in the input only mode with the internal pull-up disabled. the oper ation of port 0 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to section 8.13.1 ? port configurations ? and table 11 ? static characteristics ? for details. the keypad interrupt feature operates with port 0 pins. all pins have schmitt trigger inputs. port 0 also provides various special functions as described below: p0.0/cmp2/ kbi0/ad01 327i/o p0.0 ? port 0 bit 0. o cmp2 ? comparator 2 output. i kbi0 ? keyboard input 0. i ad01 ? adc0 channel 1 analog input. (p89lpc935/936) p0.1/cin2b/ kbi1/ad10 26 22 i/o p0.1 ? port 0 bit 1. i cin2b ? comparator 2 positive input b. i kbi1 ? keyboard input 1. i ad10 ? adc1 channel 0 analog input. p0.2/cin2a/ kbi2/ad11 25 21 i/o p0.2 ? port 0 bit 2. i cin2a ? comparator 2 positive input a. i kbi2 ? keyboard input 2. i ad11 ? adc1 channel 1 analog input. p0.3/cin1b/ kbi3/ad12 24 20 i/o p0.3 ? port 0 bit 3. i cin1b ? comparator 1 positive input b. i kbi3 ? keyboard input 3. i ad12 ? adc1 channel 2 analog input. p0.4/cin1a/ kbi4/dac1/ ad13 23 19 i/o p0.4 ? port 0 bit 4. i cin1a ? comparator 1 positive input a. i kbi4 ? keyboard input 4. o dac1 ? digital-to-analog converter output 1. i ad13 ? adc1 channel 3 analog input. p0.5/ cmpref/ kbi5 22 18 i/o p0.5 ? port 0 bit 5. i cmpref ? comparator reference (negative) input. i kbi5 ? keyboard input 5. p0.6/cmp1/ kbi6 20 16 i/o p0.6 ? port 0 bit 6. o cmp1 ? comparator 1 output. i kbi6 ? keyboard input 6. p0.7/t1/ kbi7 19 15 i/o p0.7 ? port 0 bit 7. i/o t1 ? timer/counter 1 external count input or overflow output. i kbi7 ? keyboard input 7.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 8 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core p1.0 to p1.7 i/o, i [1] port 1: port 1 is an 8-bit i/o port wit h a user-configurable output type, except for three pins as noted below. during reset port 1 latches are configured in the input only mode with the internal pull-up disabled. the operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. ea ch of the configurable port pins are programmed independently. refer to section 8.13.1 ? port configurations ? and table 11 ? static characteristics ? for details. p1.2 and p1.3 are open drain when used as outputs. p1.5 is input only. all pins have schmitt trigger inputs. port 1 also provides various special functions as described below: p1.0/txd 18 14 i/o p1.0 ? port 1 bit 0. o txd ? transmitter output for the serial port. p1.1/rxd 17 13 i/o p1.1 ? port 1 bit 1. i rxd ? receiver input for the serial port. p1.2/t0/scl 12 8 i/o p1.2 ? port 1 bit 2 (open-drain when used as output). i/o t0 ? timer/counter 0 external count inpu t or overflow output (open-drain when used as output). i/o scl ? i 2 c serial clock input/output. p1.3/int0 / sda 11 7 i/o p1.3 ? port 1 bit 3 (open-drain when used as output). i int0 ? external interrupt 0 input. i/o sda ? i 2 c serial data input/output. p1.4/int1 10 6 i p1.4 ? port 1 bit 4. i int1 ? external interrupt 1 input. p1.5/rst 62i p1.5 ? port 1 bit 5 (input only). i rst ? external reset input during power-on or if selected via ucfg1. when functioning as a reset input, a low on this pin resets the microcontroller, causing i/o ports and peripherals to take on their default states, and the processor begins execut ion at address 0. also used during a power-on sequence to force isp mode. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until vdd has reached its specified level. when system power is removed vdd will fall below the minimum specified operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when vdd falls below the minimum specified operating voltage. p1.6/ocb 5 1 i/o p1.6 ? port 1 bit 6. o ocb ? output compare b. (p89lpc935/936) p1.7/occ/ ad00 428i/o p1.7 ? port 1 bit 7. o occ ? output compare c. (p89lpc935/936) i ad00 ? adc0 channel 0 analog input. (p89lpc935/936) table 4. pin description ?continued symbol pin type description tssop28, plcc28 hvqfn28
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 9 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core p2.0 to p2.7 i/o port 2: port 2 is an 8-bit i/o port wit h a user-configurable output type. during reset port 2 latches are configured in the input only mode with the internal pull-up disabled. the oper ation of port 2 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to section 8.13.1 ? port configurations ? and table 11 ? static characteristics ? for details. all pins have schmitt trigger inputs. port 2 also provides various special functions as described below: p2.0/icb/ dac0/ad03 125i/o p2.0 ? port 2 bit 0. i icb ? input capture b. (p89lpc935/936) i dac0 ? digital-to-analog converter output. i ad03 ? adc0 channel 3 analog input. (p89lpc935/936) p2.1/ocd/ ad02 226i/o p2.1 ? port 2 bit 1. o ocd ? output compare d. (p89lpc935/936) i ad02 ? adc0 channel 2 analog input. (p89lpc935/936) p2.2/mosi 13 9 i/o p2.2 ? port 2 bit 2. i/o mosi ? spi master out slave in. when conf igured as master, this pin is output; when configured as slave, this pin is input. p2.3/miso 14 10 i/o p2.3 ? port 2 bit 3. i/o miso ? when configured as master, this pin is input, when configured as slave, this pin is output. p2.4/ss 15 11 i/o p2.4 ? port 2 bit 4. i ss ? spi slave select. p2.5/ spiclk 16 12 i/o p2.5 ? port 2 bit 5. i/o spiclk ? spi clock. when configured as master, this pin is output; when configured as slave, this pin is input. p2.6/oca 27 23 i/o p2.6 ? port 2 bit 6. o oca ? output compare a. (p89lpc935/936) p2.7/ica 28 24 i/o p2.7 ? port 2 bit 7. i ica ? input capture a. (p89lpc935/936) table 4. pin description ?continued symbol pin type description tssop28, plcc28 hvqfn28
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 10 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] input/output for p1.0 to p1.4, p1.6, p1.7. input for p1.5. p3.0 to p3.1 i/o port 3: port 3 is a 2-bit i/o port with a user-configurable output type. during reset port 3 latches are configured in the input only mode with the internal pull-up disabled. the oper ation of port 3 pins as inputs and outputs depends upon the port configuration selected. each port pin is configured independently. refer to section 8.13.1 ? port configurations ? and table 11 ? static characteristics ? for details. all pins have schmitt trigger inputs. port 3 also provides various special functions as described below: p3.0/xtal2/ clkout 95i/o p3.0 ? port 3 bit 0. o xtal2 ? output from the oscillator ampl ifier (when a crystal oscillator option is selected via the flash configuration. o clkout ? cpu clock divided by 2 when enabled via sfr bit (enclk - trim.6). it can be used if the cpu clock is the internal rc oscillator, watchdog oscillator or external clock input, except when xtal1/xtal2 are used to generate clock source for the rtc/system timer. p3.1/xtal1 8 4 i/o p3.1 ? port 3 bit 1. i xtal1 ? input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). it can be a port pin if internal rc oscillator or watchdog oscillator is used as the cpu clock source, and if xtal1/xtal2 are not used to gen erate the clock fo r the rtc/system timer. v ss 73i ground: 0 v reference. v dd 21 17 i power supply: this is the power supply voltage for normal operation as well as idle and power-down modes. table 4. pin description ?continued symbol pin type description tssop28, plcc28 hvqfn28
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 11 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 7. logic symbols fig 6. p89lpc933/934 logic symbol v dd v ss port 0 port 3 txd rxd t0 int0 int1 rst scl sda 002aab077 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 dac1 dac0 mosi miso ss spiclk ad10 ad11 ad12 ad13 port 1 port 2 p89lpc933 p89lpc934 clkout fig 7. p89lpc935/936 logic symbol v dd v ss port 0 port 3 txd rxd t0 int0 int1 rst scl sda 002aab078 cmp2 cin2b cin2a cin1b cin1a cmpref cmp1 t1 xtal2 xtal1 kbi0 kbi1 kbi2 kbi3 kbi4 kbi5 kbi6 kbi7 dac1 mosi miso ss spiclk ad10 ad11 ad12 ad13 ad01 port 1 port 2 p89lpc935 p89lpc936 ocb occ icb ocd oca ica ad00 ad03 ad02 dac0 clkout
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 12 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8. functional description remark: please refer to the p89lpc933/934/935/936 user manual for a more detailed functional description. 8.1 special function registers remark: sfr accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not defined. ? accesses to any defined sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled ?-?, logic 0 or logic 1 can only be written and read as follows: ? ?-? unless otherwise specified, must be written with logic 0, but can return any value when read (even if it was written with logic 0). it is a reserved bit and may be used in future derivatives. ? logic 0 must be written with logic 0, and will return a logic 0 when read. ? logic 1 must be written with logic 1, and will return a logic 1 when read.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 13 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core table 5. special function registers - p89lpc933/934 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit addresse7e6e5e4e3e2e1e0 acc* accumulator e0h 00 0000 0000 adcon0a/d control register0 8eh-----enadc0--0000000000 adcon1 a/d control register 1 97h enbi1 enadci 1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 0000 0000 adinsa/d input select a3hadi13adi12adi11adi10----0000000000 admodaa/d mode registera c0hbndi1burst1scc1scan1----0000000000 admodb a/d mode register b a1h clk2 clk1 clk0 - endac1 endac0 bsa1 - 00 000x 0000 ad0dat3 a/d_0 data register 3 f4h 00 0000 0000 ad1bh a/d_1 boundary high register c4h ff 1111 1111 ad1bl a/d_1 boundary low register bch 00 0000 0000 ad1dat0 a/d_1 data register 0 d5h 00 0000 0000 ad1dat1 a/d_1 data register 1 d6h 00 0000 0000 ad1dat2 a/d_1 data register 2 d7h 00 0000 0000 ad1dat3 a/d_1 data register 3 f5h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 [1] 0000 00x0 bit addressf7f6f5f4f3f2f1f0 b* b register f0h 00 0000 0000 brgr0 baud rate generator rate low beh 00 [2] 0000 0000 brgr1 baud rate generator rate high bfh 00 [1] [2] 0000 0000 brgconbaud rate generator controlbdh------sbrgsbrgen00 [2] xxxx xx00 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [1] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [1] xx00 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program flash address high e7h 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 14 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fmadrl program flash address low e6h 00 0000 0000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 0000 0000 i2adr i 2 c slave address register dbh i2adr.6 i2adr.5 i 2adr.4 i2adr.3 i2adr.2 i2a dr.1 i2adr.0 gc 00 0000 0000 bit addressdfdedddcdbdad9 d8 i2con* i 2 c control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 icrah input capture a register high abh 00 0000 0000 icral input capture a register low aah 00 0000 0000 icrbh input capture b register high afh 00 0000 0000 icrbl input capture b register low aeh 00 0000 0000 bit addressafaeadacabaaa9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 0000 bit addressefeeedecebeae9 e8 ien1* interrupt enable 1 e8h ead est - - espi ec ekbi ei2c 00 [3] 00x0 0000 bit addressbfbebdbcbbbab9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [3] x000 0000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [3] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h pad pst - - pspi pc pkbi pi2c 00 [3] 00x0 0000 ip1h interrupt priority 1 high f7h padh psth - - pspih pch pkbih pi2ch 00 [3] 00x0 0000 table 5. special function registers - p89lpc933/934 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 15 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core kbconkeypad control register94h------patn _sel kbif 00 [3] xxxx xx00 kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 bit address8786858483828180 p0* port 0 80h t1/kb7 cmp1 /kb6 cmpref /kb5 cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [3] bit address9796959493929190 p1* port 1 90h - - rst int1 int0 / sda t0/scl rxd txd [3] bit addressa7a6a5a4a3a2a1a0 p2* port 2 a0h - - spiclk ss miso mosi - - [3] bit addressb7b6b5b4b3b2b1b0 p3*port3 b0h------xtal1xtal2 [3] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1. 5) (p0m1.4) (p0m1.3) (p0m 1.2) (p0m1.1) (p0m1.0) ff [3] 1111 1111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2. 5) (p0m2.4) (p0m2.3) (p0m 2.2) (p0m2.1) (p0m2.0) 00 [3] 0000 0000 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - ( p1m1.4) (p1m1.3) (p1m1.2 )(p1m1.1)(p1m1.0)d3 [3] 11x1 xx11 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - ( p1m2.4) (p1m2.3) (p1m2.2 )(p1m2.1)(p1m2.0)00 [3] 00x0 xx00 p2m1 port 2 output mode 1 a4h (p2m1.7) (p2m1.6) (p2m1. 5) (p2m1.4) (p2m1.3) (p2m 1.2) (p2m1.1) (p2m1.0) ff [3] 1111 1111 p2m2 port 2 output mode 2 a5h (p2m2.7) (p2m2.6) (p2m2. 5) (p2m2.4) (p2m2.3) (p2m 2.2) (p2m2.1) (p2m2.0) 00 [3] 0000 0000 p3m1port3 output mode1 b1h------(p3m1.1)(p3m1.0)03 [3] xxxx xx11 p3m2port3 output mode2 b2h------(p3m2.1)(p3m2.0)00 [3] xxxx xx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd - vcpd adpd i2pd sppd spd - 00 [3] 0000 0000 bit addressd7d6d5d4d3d2d1d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [4] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [3] [5] 011x xx00 table 5. special function registers - p89lpc933/934 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 16 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core rtch real-time clock register high d2h 00 [5] 0000 0000 rtcl real-time clock register low d3h 00 [5] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address9f9e9d9c9b9a99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 0000 0100 spstat spi status register e1h spif wcol - - ----0000xx xxxx spdat spi data register e3h 00 0000 0000 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0 xxx0 bit address8f8e8d8c8b8a89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 0000 0000 trim internal oscillator trim register 96h rccl k enclk trim.5 trim.4 trim. 3 trim.2 trim.1 trim.0 [6] [5] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [7] [5] table 5. special function registers - p89lpc933/934 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 17 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] unimplemented bits in sfrs (labeled ?-?) are x (unknown) at all times. unless other wise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. the rese t values shown for these bits are log ic 0s although they are unknown when read. [2] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpr edictable. [3] all ports are in input only (high-impedance) state after power-up. [4] the rstsrc register reflects the cause of the p89lpc933/934/ 935/936 reset. upon a power-up reset, all reset source flags are cleared except pof and bof; the power-on reset value is xx11 0000. [5] the only reset source that affects these sfrs is power-on reset. [6] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [7] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are al l logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watc hdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 5. special function registers - p89lpc933/934 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 18 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core table 6. special function registers - p89lpc935/936 * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary bit addresse7e6e5e4e3e2e1e0 acc* accumulator e0h 00 0000 0000 adcon0 a/d control register 0 8eh enbi0 enadci 0 tmm0 edge0 adci0 enadc0 adcs01 adcs00 00 0000 0000 adcon1 a/d control register 1 97h enbi1 enadci 1 tmm1 edge1 adci1 enadc1 adcs11 adcs10 00 0000 0000 adins a/d input select a3h adi13 adi12 adi11 adi10 adi03 adi02 adi01 adi00 00 0000 0000 admoda a/d mode register a c0h bndi1 burst1 scc1 scan1 bndi0 burst0 scc0 scan0 00 0000 0000 admodb a/d mode register b a1h clk2 clk1 clk0 - endac1 endac0 bsa1 bsa0 00 000x 0000 ad0bh a/d_0 boundary high register bbh ff 1111 1111 ad0bl a/d_0 boundary low register a6h 00 0000 0000 ad0dat0 a/d_0 data register 0 c5h 00 0000 0000 ad0dat1 a/d_0 data register 1 c6h 00 0000 0000 ad0dat2 a/d_0 data register 2 c7h 00 0000 0000 ad0dat3 a/d_0 data register 3 f4h 00 0000 0000 ad1bh a/d_1 boundary high register c4h ff 1111 1111 ad1bl a/d_1 boundary low register bch 00 0000 0000 ad1dat0 a/d_1 data register 0 d5h 00 0000 0000 ad1dat1 a/d_1 data register 1 d6h 00 0000 0000 ad1dat2 a/d_1 data register 2 d7h 00 0000 0000 ad1dat3 a/d_1 data register 3 f5h 00 0000 0000 auxr1 auxiliary function register a2h clklp ebrr ent1 ent0 srst 0 - dps 00 0000 00x0 bit addressf7f6f5f4f3f2f1f0 b* b register f0h 00 0000 0000 brgr0 [2] baud rate generator rate low beh 00 0000 0000 brgr1 [2] baud rate generator rate high bfh 00 0000 0000 brgconbaud rate generator controlbdh------sbrgsbrgen00 [2] xxxx xx00 cccra capture compare a control register eah iceca2 iceca1 iceca0 icesa icnfa fcoa ocma1 ocma0 00 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 19 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core cccrb capture compare b control register ebh icecb2 icecb1 icecb0 icesb icnfb fcob ocmb1 ocmb0 00 0000 0000 cccrc capture compare c control register ech-----fcococmc1ocmc000 xxxx x000 cccrd capture compare d control register edh-----fcodocmd1ocmd000 xxxx x000 cmp1 comparator 1 control register ach - - ce1 cp1 cn1 oe1 co1 cmf1 00 [3] xx00 0000 cmp2 comparator 2 control register adh - - ce2 cp2 cn2 oe2 co2 cmf2 00 [3] xx00 0000 deecon data eeprom control register f1h eeif hverr ectl1 ectl0 - - - eadr8 0e 0000 1110 deedat data eeprom data register f2h 00 0000 0000 deeadr data eeprom address register f3h 00 0000 0000 divm cpu clock divide-by-m control 95h 00 0000 0000 dptr data pointer (2 bytes) dph data pointer high 83h 00 0000 0000 dpl data pointer low 82h 00 0000 0000 fmadrh program flash address high e7h 00 0000 0000 fmadrl program flash address low e6h 00 0000 0000 fmcon program flash control (read) e4h busy - - - hva hve sv oi 70 0111 0000 program flash control (write) e4h fmcmd. 7 fmcmd. 6 fmcmd. 5 fmcmd. 4 fmcmd. 3 fmcmd. 2 fmcmd. 1 fmcmd. 0 fmdata program flash data e5h 00 0000 0000 i2adr i 2 c slave address register dbh i2adr.6 i2adr.5 i 2adr.4 i2adr.3 i2adr.2 i2a dr.1 i2adr.0 gc 00 0000 0000 bit addressdfdedddcdbdad9 d8 i2con* i 2 c control register d8h - i2en sta sto si aa - crsel 00 x000 00x0 i2dat i 2 c data register dah i2sclh serial clock generator/scl duty cycle register high ddh 00 0000 0000 table 6. special function registers - p89lpc935/936 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 20 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core i2scll serial clock generator/scl duty cycle register low dch 00 0000 0000 i2stat i 2 c status register d9h sta.4 sta.3 sta.2 sta.1 sta.0 0 0 0 f8 1111 1000 icrah input capture a register high abh 00 0000 0000 icral input capture a register low aah 00 0000 0000 icrbh input capture b register high afh 00 0000 0000 icrbl input capture b register low aeh 00 0000 0000 bit addressafaeadacabaaa9 a8 ien0* interrupt enable 0 a8h ea ewdrt ebo es/esr et1 ex1 et0 ex0 00 0000 0000 bit addressefeeedecebeae9 e8 ien1* interrupt enable 1 e8h eadee est - eccu espi ec ekbi ei2c 00 [3] 00x0 0000 bit addressbfbebdbcbbbab9 b8 ip0* interrupt priority 0 b8h - pwdrt pbo ps/psr pt1 px1 pt0 px0 00 [3] x000 0000 ip0h interrupt priority 0 high b7h - pwdrt h pboh psh/ psrh pt1h px1h pt0h px0h 00 [3] x000 0000 bit address ff fe fd fc fb fa f9 f8 ip1* interrupt priority 1 f8h padee pst - pccu pspi pc pkbi pi2c 00 [3] 00x0 0000 ip1h interrupt priority 1 high f7h paeeh psth - pccuh pspih pch pkbih pi2ch 00 [3] 00x0 0000 kbconkeypad control register94h------patn _sel kbif 00 [3] xxxx xx00 kbmask keypad interrupt mask register 86h 00 0000 0000 kbpatn keypad pattern register 93h ff 1111 1111 ocrah output compare a register high efh 00 0000 0000 ocral output compare a register low eeh 00 0000 0000 ocrbh output compare b register high fbh 00 0000 0000 ocrbl output compare b register low fah 00 0000 0000 table 6. special function registers - p89lpc935/936 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 21 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core ocrch output compare c register high fdh 00 0000 0000 ocrcl output compare c register low fch 00 0000 0000 ocrdh output compare d register high ffh 00 0000 0000 ocrdl output compare d register low feh 00 0000 0000 bit address8786858483828180 p0* port 0 80h t1/kb7 cmp1 /kb6 cmpref /kb5 cin1a /kb4 cin1b /kb3 cin2a /kb2 cin2b /kb1 cmp2 /kb0 [3] bit address9796959493929190 p1* port 1 90h occ ocb rst int1 int0 / sda t0/scl rxd txd [3] bit addressa7a6a5a4a3a2a1a0 p2* port 2 a0h ica oca spiclk ss miso mosi ocd icb [3] bit addressb7b6b5b4b3b2b1b0 p3*port3 b0h------xtal1xtal2 [3] p0m1 port 0 output mode 1 84h (p0m1.7) (p0m1.6) (p0m1. 5) (p0m1.4) (p0m1.3) (p0m 1.2) (p0m1.1) (p0m1.0) ff [3] 1111 1111 p0m2 port 0 output mode 2 85h (p0m2.7) (p0m2.6) (p0m2. 5) (p0m2.4) (p0m2.3) (p0m 2.2) (p0m2.1) (p0m2.0) 00 [3] 0000 0000 p1m1 port 1 output mode 1 91h (p1m1.7) (p1m1.6) - ( p1m1.4) (p1m1.3) (p1m1.2 )(p1m1.1)(p1m1.0)d3 [3] 11x1 xx11 p1m2 port 1 output mode 2 92h (p1m2.7) (p1m2.6) - ( p1m2.4) (p1m2.3) (p1m2.2 )(p1m2.1)(p1m2.0)00 [3] 00x0 xx00 p2m1 port 2 output mode 1 a4h (p2m1.7) (p2m1.6) (p2m1. 5) (p2m1.4) (p2m1.3) (p2m 1.2) (p2m1.1) (p2m1.0) ff [3] 1111 1111 p2m2 port 2 output mode 2 a5h (p2m2.7) (p2m2.6) (p2m2. 5) (p2m2.4) (p2m2.3) (p2m 2.2) (p2m2.1) (p2m2.0) 00 [3] 0000 0000 p3m1port3 output mode1 b1h------(p3m1.1)(p3m1.0)03 [3] xxxx xx11 p3m2port3 output mode2 b2h------(p3m2.1)(p3m2.0)00 [3] xxxx xx00 pcon power control register 87h smod1 smod0 bopd boi gf1 gf0 pmod1 pmod0 00 0000 0000 pcona power control register a b5h rtcpd deepd vcpd adpd i2pd sppd spd ccupd 00 [3] 0000 0000 bit addressd7d6d5d4d3d2d1d0 psw* program status word d0h cy ac f0 rs1 rs0 ov f1 p 00 0000 0000 pt0ad port 0 digital input disable f6h - - pt0ad.5 pt0ad.4 pt0ad.3 pt0ad.2 pt0ad.1 - 00 xx00 000x table 6. special function registers - p89lpc935/936 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 22 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core rstsrc reset source register dfh - - bof pof r_bk r_wd r_sf r_ex [4] rtccon real-time clock control d1h rtcf rtcs1 rtcs0 - - - ertc rtcen 60 [3] [5] 011x xx00 rtch real-time clock register high d2h 00 [5] 0000 0000 rtcl real-time clock register low d3h 00 [5] 0000 0000 saddr serial port address register a9h 00 0000 0000 saden serial port address enable b9h 00 0000 0000 sbuf serial port data buffer register 99h xx xxxx xxxx bit address9f9e9d9c9b9a99 98 scon* serial port control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00 0000 0000 sstat serial port extended status register bah dbmod intlo cidis dbisel fe br oe stint 00 0000 0000 sp stack pointer 81h 07 0000 0111 spctl spi control register e2h ssig spen dord mstr cpol cpha spr1 spr0 04 0000 0100 spstat spi status register e1h spif wcol - - ----0000xx xxxx spdat spi data register e3h 00 0000 0000 tamod timer 0 and 1 auxiliary mode 8fh - - - t1m2 - - - t0m2 00 xxx0 xxx0 bit address8f8e8d8c8b8a89 88 tcon* timer 0 and 1 control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00 0000 0000 tcr20* ccu control register 0 c8h pleen hltrn hlten altcd altab tdir2 tmod21 tmod20 00 0000 0000 tcr21 ccu control register 1 f9h tcou2 - - - plldv.3 plldv.2 plldv.1 plldv.0 00 0xxx 0000 th0 timer 0 high 8ch 00 0000 0000 th1 timer 1 high 8dh 00 0000 0000 th2 ccu timer high cdh 00 0000 0000 ticr2 ccu interrupt control register c9h toie2 tocie2 d tocie2 c tocie2b tocie2a - ticie2b ticie2a 00 0000 0x00 tifr2 ccu interrupt flag register e9h toif2 tocf2d tocf2c tocf2b tocf2a - ticf2b ticf2a 00 0000 0x00 tise2 ccu interrupt status encode register deh-----encint. 2 encint. 1 encint. 0 00 xxxx x000 tl0 timer 0 low 8ah 00 0000 0000 tl1 timer 1 low 8bh 00 0000 0000 table 6. special function registers - p89lpc935/936 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 23 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] unimplemented bits in sfrs (labeled ?-?) are x (unknown) at all times. unless other wise specified, ones should not be written to these bits since they may be used for other purposes in future derivatives. the rese t values shown for these bits are log ic 0s although they are unknown when read. [2] all ports are in input only (high-impedance) state after power-up. [3] brgr1 and brgr0 must only be written if brgen in brgcon sfr is logic 0. if any are written while brgen = 1, the result is unpr edictable. [4] the rstsrc register reflects the cause of the p89lpc933/934/ 935/936 reset. upon a power-up reset, all reset source flags are cleared except pof and bof; the power-on reset value is xx11 0000. [5] after reset, the value is 1110 01x1, i.e., pre2 to pre0 are al l logic 1, wdrun = 1 and wdclk = 1. wdtof bit is logic 1 after watc hdog reset and is logic 0 after power-on reset. other resets will not affect wdtof. [6] on power-on reset, the trim sfr is initialized with a factory preprogrammed value. other resets will not cause initializatio n of the trim register. [7] the only reset source that affects these sfrs is power-on reset. tl2 ccu timer low cch 00 0000 0000 tmod timer 0 and 1 mode 89h t1gate t1c/t t1m1 t1m0 t0gate t0c/t t0m1 t0m0 00 0000 0000 tor2h ccu reload register high cfh 00 0000 0000 tor2l ccu reload register low ceh 00 0000 0000 tpcr2hprescaler control register highcbh------tpcr2h. 1 tpcr2h. 0 00 xxxx xx00 tpcr2l prescaler control register low cah tpcr2l. 7 tpcr2l. 6 tpcr2l. 5 tpcr2l. 4 tpcr2l. 3 tpcr2l. 2 tpcr2l. 1 tpcr2l. 0 00 0000 0000 trim internal oscillator trim register 96h rccl k enclk trim.5 trim.4 trim. 3 trim.2 trim.1 trim.0 [6] [5] wdcon watchdog control register a7h pre2 pre1 pre0 - - wdrun wdtof wdclk [7] [5] wdl watchdog load c1h ff 1111 1111 wfeed1 watchdog feed 1 c2h wfeed2 watchdog feed 2 c3h table 6. special function registers - p89lpc935/936 ?continued * indicates sfrs that are bit addressable. name description sfr addr. bit functions and addresses reset value msb lsb hex binary
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 24 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.2 enhanced cpu the p89lpc933/934/935/936 uses an enhanced 80c51 cpu which runs at six times the speed of standard 80c51 devices. a machine cycle consists of two cpu clock cycles, and most instructions execute in one or two machine cycles. 8.3 clocks 8.3.1 clock definitions the p89lpc933/934/935/936 device has several internal clocks as defined below: oscclk ? input to the divm clock divider. oscclk is selected from one of four clock sources (see figure 8 ) and can also be optionally divided to a slower frequency (see section 8.8 ? cclk modification: divm register ? ). remark: f osc is defined as the oscclk frequency. cclk ? cpu clock; output of the clock divider. there are two cclk cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four cclk cycles). rcclk ? the internal 7.373 mhz rc oscillator output. pclk ? clock for the various peripheral devices and is cclk ? 2 . 8.3.2 cpu clock (oscclk) the p89lpc933/934/935/ 936 provides several user-sel ectable oscillator options in generating the cpu clock. this allows opti mization for a range of needs from high precision to lowest possible cost. these options are configured when the flash is programmed and incl ude an on-chip watchdog oscillator, an on-chip rc oscillator, an oscillator using an external crystal, or an ex ternal clock source. the crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 khz to 18 mhz. 8.3.3 low speed oscillator option this option supports an external crystal in the range of 20 khz to 100 khz. ceramic resonators are also supported in this configuration. 8.3.4 medium speed oscillator option this option supports an external crystal in the range of 100 khz to 4 mhz. ceramic resonators are also supported in this configuration. 8.3.5 high speed oscillator option this option supports an external crystal in the range of 4 mhz to 18 mhz. ceramic resonators are also supported in this configuration. 8.3.6 clock output the p89lpc933/934/935/936 supports a user-s electable clock output function on the xtal2/clkout pin when crystal oscillator is not being used. this condition occurs if another clock source has been selected (on-chip rc osc illator, watchdog oscillator,
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 25 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core external clock input on x1) and if the rtc is not using the crystal oscillator as its clock source. this allows external devices to syn chronize to the p89lpc933/934/935/936. this output is enabled by the enclk bit in the trim register. the frequency of this clock output is 1 ? 2 that of the cclk. if th e clock output is not needed in idle mode, it may be turned off prior to entering idle, saving additional power. 8.4 on-chip rc oscillator option the p89lpc933/934/935/936 has a 6-bit trim register that can be used to tune the frequency of the rc oscillator. during reset, the trim value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 mhz 1 % at room temperature. end-user applications can write to the trim register to adjust the on-chip rc oscillator to ot her frequencies. 8.5 watchdog oscillator option the watchdog has a separate oscillator which has a frequen cy of 400 khz. this oscillator can be used to save power when a high clock frequency is not needed. 8.6 external clock input option in this configuration, the processor clock is derived from an external source driving the p3.1/xtal1 pin. the rate may be from 0 hz up to 18 mhz. the p3.0/xtal2 pin may be used as a standard port pin or a clock output. when using an oscillator frequency above 12 mhz, the reset input function of p1.5 must be enabled. an external circuit is required to hold the device in reset at power-up until vdd has reached its specified level. when system power is removed vdd will fall below the minimum specified operating voltage. when using an oscillator frequency above 12 mhz, in some applications, an external brownout detect circuit may be required to hold the device in reset when v dd falls below the minimum specified operating voltage.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 26 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 8. block diagram of oscillator control 2 002aab079 rtc adc1 adc0 (p89lpc935/936) cpu wdt divm cclk uart oscclk i 2 c-bus pclk timer 0 and timer 1 high frequency medium frequency low frequency xtal1 xtal2 rc oscillator watchdog oscillator (7.3728 mhz 1 %) pclk rcclk spi ccu (p89lpc935/936) 32 pll (400 khz + 30 % ? 20 %)
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 27 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.7 cclk wake-up delay the p89lpc933/934/935/936 has an internal wa ke-up timer that delays the clock until it stabilizes depending on the clock source used. if the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 oscclk cycles plus 60 sto100 s. if the clock source is either the internal rc oscillator, watchdog oscillator, or external clock, the delay is 22 4 oscclk cycles plus 60 s to 100 s. 8.8 cclk modificati on: divm register the oscclk frequency can be divided down up to 510 times by configuring a dividing register, divm, to generate ccl k. this feature makes it poss ible to temporarily run the cpu at a lower rate, reducing power consumption. by dividing the clock, the cpu can retain the ability to respond to events that would not exit idle mode by executing its normal program at a lower rate. this can also allow by passing the oscillator start-up time in cases where power-down mode would otherwise be used. the value of divm may be changed by the program at any time with out interrupting code execution. 8.9 low power select the p89lpc933/934/935/936 is designed to ru n at 18 mhz (cclk) maximum. however, if cclk is 8 mhz or slower, the clklp sfr bit (auxr1.7) can be set to logic 1 to lower the power consumption further. on any reset, clklp is logic 0 allowing highest performance access. this bit can then be set in software if cclk is running at 8 mhz or slower. 8.10 memory organization the various p89lpc933/934/935/936 memory spaces are as follows: ? data 128 bytes of internal data memory space (00h:7fh) accessed via direct or indirect addressing, using instructions other than movx and movc. all or part of the stack may be in this area. ? idata indirect data. 256 bytes of internal da ta memory space (00h:ffh) accessed via indirect addressing using instructions othe r than movx and movc. all or part of the stack may be in this area. this area includes the data area and the 128 bytes immediately above it. ? sfr selected cpu registers and peripheral contro l and status registers, accessible only via direct addressing. ? xdata (p89lpc935/936) ?external? data or au xiliary ram. duplicates the cl assic 80c51 64 kb memory space addressed via the movx instruction using th e sptr, r0, or r1. all or part of this space could be implemented on-chip. the p89lpc935/936 has 512 bytes of on-chip xdata memory.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 28 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core ? code 64 kb of code memory space, accessed as part of program execution and via the movc instruction. the p89lpc933/934/935/ 936 have 4 kb/8 kb/16 kb of on-chip code memory. the p89lpc935/936 also has 512 bytes of on-chip data eeprom that is accessed via sfrs (see section 8.27 ? data eeprom (p89lpc935/936) ? ). 8.11 data ram arrangement the 768 bytes of on-chip ram are organized as shown in ta b l e 7 . 8.12 interrupts the p89lpc933/934/935/936 uses a four priori ty level interrupt structure. this allows great flexibility in controlling the handlin g of the many inte rrupt sources. the p89lpc933/934/935/936 supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port tx, serial port rx , combined serial port rx/tx, brownout detect, watchdog/real-time clock, i 2 c-bus, keyboard, comparators 1 and 2, spi, ccu, data eeprom write/adc completion. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers ien0 or ien1. the ien0 register also contains a global disable bit, ea, which disables all interrupts. each interrupt source can be individually pr ogrammed to one of four priority levels by setting or clearing bits in the interrupt priori ty registers ip0, ip0h, ip1, and ip1h. an interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt so urce. if two requests of different priority levels are pending at the start of an instructio n, the request of higher priority level is serviced. if requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. remark: the arbitration ranking is only used to resolve pending requests of the same priority level. 8.12.1 external interrupt inputs the p89lpc933/934/935/936 has two external interrupt inputs as well as the keypad interrupt function. the two interrupt inputs are identical to those present on the standard 80c51 microcontrollers. table 7. on-chip data memory usages type data ram size (bytes) data memory that can be address ed directly and indirectly 128 idata memory that can be addressed indirectly 256 xdata auxiliary (?external data?) on-chip memory that is accessed using the movx instructions (p89lpc935/936) 512
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 29 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core these external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit it1 or it0 in register tcon. in edge-triggered mode, if successive samples of the intn pin show a high in one cycle and a low in the next cycle, the interrupt request flag ien in tcon is set, causing an interrupt request. if an external interrupt is enabled when the p89lpc933/934/935/936 is put into power-down or idle mode, the interrupt will c ause the processor to wake-up and resume operation. refer to section 8.15 ? power reduction modes ? for details. (1) see section 8.19 ? ccu (p89lpc935/936) ? (2) p89lpc935/936 fig 9. interrupt sources, interrupt enables, and power-down wake-up sources 002aab081 ie0 ex0 ie1 ex1 bof ebo kbif ekbi interrupt to cpu wake-up (if in power-down) ewdrt cmf2 cmf1 ec ea (ie0.7) tf1 et1 ti & ri/ri es/esr ti est si ei2c spif espi rtcf ertc (rtccon.1) wdovf tf0 et0 any ccu interrupt (1) eccu enadci0 (2) adci0 (2) enadci1 adci1 enbi0 (2) bndi0 (2) enbi1 bndi1 eeif (2) eadee (p89lpc935) ead (p89lpc933/934)
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 30 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.13 i/o ports the p89lpc933/934/935/936 has four i/o po rts: port 0, port 1, port 2, and port 3. ports 0, 1 and 2 are 8-bit ports, and port 3 is a 2-bit port. the exact number of i/o pins available depends upon the clock and reset options chosen, as shown in ta b l e 8 . [1] required for operation above 12 mhz. 8.13.1 port configurations all but three i/o port pins on the p89lpc933 /934/935/936 may be configured by software to one of four types on a bit-by-bit basis. these are: quasi-bidirectional (standard 80c51 port outputs), push-pull, open drain, and inpu t-only. two configuration registers for each port select the output type for each port pin. 1. p1.5 (rst ) can only be an input and cannot be configured. 2. p1.2 (scl/t0) and p1.3 (sda/int0 ) may only be configured to be either input-only or open-drain. 8.13.1.1 quasi-bidirectional output configuration quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. this is possible beca use when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when the pin is driven low, it is driven strongly and able to sink a fairly large current. these features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. the p89lpc933/934/935/936 is a 3 v devi ce, but the pins are 5 v-tolerant. in quasi-bidirectional mode, if a user applies 5 v on the pin, there will be a current flowing from the pin to v dd , causing extra power consumption. therefore, applying 5 v in quasi-bidirectional mode is discouraged. a quasi-bidirectional port pin has a schmitt tri gger input that also has a glitch suppression circuit. 8.13.1.2 open-drain output configuration the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port la tch contains a logic 0. to be used as a logic output, a port configured in this manner must ha ve an external pull-up, typically a resistor tied to v dd . table 8. number of i/o pins available clock source reset option number of i/o pins (28-pin package) on-chip oscillator or watchdog oscillator no external reset (except during power-up) 26 external rst pin supported 25 external clock input no external reset (except during power-up) 25 external rst pin supported [1] 24 low/medium/high speed oscillator (external crystal or resonator) no external reset (except during power-up) 24 external rst pin supported [1] 23
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 31 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core an open-drain port pin has a schmitt trigger input that also has a glitch suppression circuit. 8.13.1.3 input-only configuration the input-only port configuration has no output drivers. it is a schm itt trigger input that also has a glitch suppression circuit. 8.13.1.4 push-pull output configuration the push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. a push-pull port pin has a schmitt trigger input that also has a glitch suppression circuit. 8.13.2 port 0 analog functions the p89lpc933/934/935/936 incorporates two an alog comparators. in order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. digital outputs are disabled by putting the port output into the input-only (high-impedance) mode. digital inputs on port 0 may be disabled through the use of the pt0ad register, bits 1:5. on any reset, pt0ad[1:5] defaults to logic 0s to enable digital functions. 8.13.3 additional port features after power-up, all pins are in input-only mode. remark: please note that this is different from the lpc76x series of devices. ? after power-up, all i/o pins except p1.5, may be configured by software. ? pin p1.5 is input only. pins p1.2 and p1.3 and are configurable for either input-only or open-drain. every output on the p89lpc933/934/935/936 has been designed to sink typical led drive current. however, there is a maximum to tal output current for all ports which must not be exceeded. please refer to ta b l e 11 ? static characteristics ? for detailed specifications. all ports pins that can function as an output ha ve slew rate controlled outputs to limit noise generated by quickly switching output sig nals. the slew rate is factory-set to approximately 10 ns rise and fall times. 8.14 power monitoring functions the p89lpc933/934/935/936 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. this is accomplished with two hardware functions: power-on detect and brownout detect.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 32 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.14.1 brownout detection the brownout detect function determines if the power supply voltage drops below a certain level. the default operation is for a br ownout detection to cause a processor reset, however it may alternatively be configured to generate an interrupt. brownout detection may be enabled or disabled in software. if brownout detection is enabled the brownout condition occurs when v dd falls below the brownout trip voltage, v bo (see table 11 ? static characteristics ? ), and is negated when v dd rises above v bo . if the p89lpc933/934/935/936 devic e is to operate with a power supply that can be below 2.7 v, boe should be left in the unprogrammed state so that the device can operate at 2.4 v, otherwise continuous br ownout reset may prevent the device from operating. for correct activation of brownout detect, the v dd rise and fall times must be observed. please see ta b l e 11 ? static characteristics ? for specifications. 8.14.2 power-on detection the power-on detect has a function similar to th e brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. the pof flag in the rstsrc register is set to indicate an initial power-up condition. the pof flag will remain set until cleared by software. 8.15 power reduction modes the p89lpc933/934/935/936 supports three different power reduction modes. these modes are idle mode, power-down mode, and total power-down mode. 8.15.1 idle mode idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. any enabled in terrupt source or reset may terminate idle mode. 8.15.2 power-down mode the power-down mode stops th e oscillator in order to mini mize power consumption. the p89lpc933/934/935/936 exits power-down mode via any reset, or certain interrupts. in power-down mode, the power supply voltage may be reduced to the ram keep-alive voltage v ram . this retains the ram contents at the point where power-down mode was entered. sfr contents are not guaranteed after v dd has been lowered to v ddr , therefore it is highly recommended to wake-up th e processor via reset in this case. v dd must be raised to within the operating range before the power-down mode is exited. some chip functions continue to operate and draw power during power-down mode, increasing the total power used during power-down. these include: brownout detect, watchdog timer, comparators (note that comp arators can be powered-down separately), and rtc/system timer. the intern al rc oscillator is disabled unless both the rc oscillator has been selected as the system clock and the rtc is enabled.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 33 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.15.3 total power-down mode this is the same as power-do wn mode except that the brow nout detection circuitry and the voltage comparators are also disabled to conserve additional power. the internal rc oscillator is disabled unless bo th the rc oscillator has been se lected as the system clock and the rtc is enabled. if the internal rc o scillator is used to clock the rtc during power-down, there will be high power consumpti on. please use an exte rnal low frequency clock to achieve low power with the rtc running during power-down. 8.16 reset the p1.5/rst pin can function as either a low-active reset input or as a digital input, p1.5. the reset pin enable (rpe) bit in ucfg1, when set to logic 1, enables the external reset input function on p1.5. when cleared, p1.5 may be used as an input pin. remark: during a power-up s equence, the rpe selection is overridden and this pin will always functions as a reset input. an external circuit connected to this pin should not hold this pin low during a power-on sequence as this will keep the device in reset. after power-up this input will function either as an external reset input or as a digital input as defined by the rpe bit. only a power-up reset will temporarily ov erride the selection defined by rpe bit. other sources of reset w ill not override the rpe bit. when this pin functions as a reset input, an internal pull-up resistance is connected (see ta b l e 11 ? static characteristics ? ). reset can be triggered from the following sources: ? external reset pin (during power-up or if user configured via ucfg1). ? power-on detect. ? brownout detect. ? watchdog timer. ? software reset. ? uart break character detect reset. for every reset source, there is a flag in the reset register, rstsrc. the user can read this register to determine the most recent re set source. these flag bits can be cleared in software by writing a logic 0 to the corresponding bit. more than one flag bit may be set: ? during a power-on reset, both pof and bof are set but the other flag bits are cleared. ? for any other reset, previously set flag bits that have no t been cleared will remain set. 8.16.1 reset vector following reset, the p89lpc933/93 4/935/936 will fetch instruct ions from either address 0000h or the boot address. the boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00h. the boot address will be used if a uart break reset oc curs, or the non -volatile boot status bit (bootstat.0) = 1, or the device is forced into isp mode during power-on (see p89lpc933/934/935/936 user manual ). otherwise, instructions will be fetched from address 0000h.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 34 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.17 timers/counters 0 and 1 the p89lpc933/934/935/936 has two general purpose counter/timers which are upward compatible with the standard 80c51 timer 0 and timer 1. both can be configured to operate either as timers or event counter. an option to automatically toggle the t0 and/or t1 pins upon timer overflow has been added. in the ?timer? function, the register is incremented every machine cycle. in the ?counter? function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled once during every machine cycle. timer 0 and timer 1 have five operating modes (modes 0, 1, 2, 3 and 6). modes 0, 1, 2 and 6 are the same for both timers/counters. mode 3 is different. 8.17.1 mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. in this mode, the timer register is configured as a 13-bit register. mode 0 operation is the same for timer 0 and timer 1. 8.17.2 mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer register are used. 8.17.3 mode 2 mode 2 configures the timer register as an 8-bit counter with automatic reload. mode 2 operation is the same for timer 0 and timer 1. 8.17.4 mode 3 when timer 1 is in mode 3 it is stopped. timer 0 in mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. when timer 1 is in mode 3 it can still be used by the se rial port as a baud rate generator. 8.17.5 mode 6 in this mode, the corresponding timer can be changed to a pwm with a full period of 256 timer clocks. 8.17.6 timer overflow toggle output timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. the same device pins that ar e used for the t0 and t1 count inputs are also used for the timer toggle outputs. the port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. 8.18 rtc/system timer the p89lpc933/934/935/936 has a simple rtc that allows a user to continue running an accurate timer while the rest of the device is powered-down. the rtc can be a wake-up or an interrupt source. the rtc is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loada ble down counter. when it reaches all logic 0s, the counter will be reloaded again and the rtcf flag will be set. the clock source for this counter can be either the cpu clock (cclk) or the xtal osc illator, provided that the xtal oscillator is
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 35 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core not being used as the cpu clock. if the xtal oscillator is used as the cpu clock, then the rtc will use cclk as its clock source. only power-on reset will reset the rtc and its associated sfrs to the default state. 8.19 ccu (p89lpc935/936) this unit features: ? a 16-bit timer with 16-bit reload on overflow. ? selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024. ? four compare/pwm outputs with selectable polarity. ? symmetrical/asymmetrical pwm selection. ? two capture inputs with event counter and digital noise rejection filter. ? seven interrupts with common interrup t vector (one overflow, two capture, four compare). ? safe 16-bit read/write via shadow registers. 8.19.1 ccu clock the ccu runs on the ccuclk, which is either pc lk in basic timer mode, or the output of a phase-locked loop (pll). the pll is desi gned to use a clock source between 0.5 mhz to 1 mhz that is multiplied by 32 to pr oduce a ccuclk between 16 mhz and 32 mhz in pwm mode (asymmetrical or symmetrical). the p ll contains a 4-bit divider to help divide pclk into a frequency between 0.5 mhz and 1 mhz. 8.19.2 ccuclk prescaling this ccuclk can further be divided down by a prescaler. the prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow. 8.19.3 basic timer operation the timer is a free-running up/down counter with a direction control bit. if the timer counting direction is changed while the counter is runnin g, the count sequence will be reversed. the timer can be written or read at any time. when a reload occurs, the ccu timer overflow interrupt flag will be set, and an interrupt generated if enabled. the 16-bit ccu timer may also be used as an 8-bit up/down timer. 8.19.4 output compare there are four output compare channels a, b, c and d. each output compare channel needs to be enabled in order to operate and the us er will have to set the associated i/o pin to the desired output mode to connect the pin. when the contents of the timer matches that of a capture compare control register , the timer output co mpare interrupt flag (tocfx) becomes set. an inte rrupt will occur if enabled. 8.19.5 input capture input capture is always enabled. each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register. the ca pture event can be programmed to be either rising or falling edge triggered. a simple noise filter can be enab led on the input capture by enabling the input
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 36 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core capture noise filter bit. if se t, the capture logic needs to se e four consecutive samples of the same value in order to recognize an edge as a capture event. an event counter can be set to delay a capture by a number of capture events. 8.19.6 pwm operation pwm operation has two main modes, symmetrical and asymmetrical. in asymmetrical pwm operation the c cu timer operates in down-counting mode regardless of the direction control bit. in symmetrical mode, the timer counts up/down alternately. the main difference from basic timer operation is the operation of the compare module, which in pwm mode is used for pwm waveform generation. as with basic timer operation, when the pwm (compare) pins are connected to the compare logic, their logic state remains unchanged. however, since bit fco is used to hold the halt value, only a compare event can change the state of the pin. fig 10. asymmetrical pwm, down-counting mode fig 11. symmetrical pwm tor2 compare value timer value non-inverted inverted 0x0000 002aaa89 3 tor2 compare value timer value non-inverted inverted 002aaa89 4 0
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 37 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.19.7 alternating output mode in asymmetrical mode, the us er can set up pwm channels a/b and c/d as alternating pairs for bridge drive control. in this mo de the output of these pwm channels are alternately gated on every counter cycle. 8.19.8 pll operation the pwm module features a pll that can be used to generate a ccuclk frequency between 16 mhz and 32 mhz. at this freque ncy the pwm module provides ultrasonic pwm frequency with 10-bit resolution provided that the crystal frequency is 1 mhz or higher. the pll is fed an input signal from 0.5 mhz to 1 mhz and generates an output signal of 32 times the input frequency. this si gnal is used to clock the timer. the user will have to set a divider that scales pclk by a factor from 1 to 16. this divider is found in the sfr register tcr21. the pll freque ncy can be expressed as shown in equation 1 . (1) where: n is the value of plldv.3 to plldv.0. since n ranges from 0 to 15, the cclk frequency can be in the range of pclk to pclk ? 16 . fig 12. alternate output mode timer value 002aaa895 0 tor2 compare value a (or c) compare value b (or d) pwm output (oca or occ) pwm output (ocb or ocd) pll frequency pclk n1 + () ----------------- - =
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 38 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.19.9 ccu interrupts there are seven interrupt sources on the ccu which share a common interrupt vector. 8.20 uart the p89lpc933/934/935/936 has an enhanced uart that is compatible with the conventional 80c51 uart except that time r 2 overflow cannot be used as a baud rate source. the p89lpc933/934/935/936 does include an independent baud rate generator. the baud rate can be selected from the os cillator (divided by a constant), timer 1 overflow, or the independent baud rate generator. in addition to the baud rate generation, enhancements over the standard 80c51 uart include framing error detection, automatic address recognition, selectable doubl e buffering and several interrupt options. the uart can be operated in four modes: shift register, 8-bit uart, 9-bit uart, and cpu clock ? 32 or cpu clock ? 16 . 8.20.1 mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted or received, lsb first. the baud rate is fixed at 1 ? 16 of the cpu clock frequency. fig 13. capture/compare unit interrupts 002aaa896 interrupt to cpu toie2 (ticr2.7) toif2 (tifr2.7) ticie2a (ticr2.0) ticf2a (tifr2.0) ticie2b (ticr2.1) ticf2b (tifr2.1) tocie2a (ticr2.3) tocf2a (tifr2.3) tocie2b (ticr2.4) tocf2b (tifr2.4) tocie2c (ticr2.5) tocf2c (tifr2.5) tocie2d (ticr2.6) tocf2d (tifr2.6) ea (ien0.7) eccu (ien1.4) priority encoder other interrupt sources encint.0 encint.1 encint.2
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 39 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.20.2 mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), and a stop bit (logic 1). when data is received, the stop bit is stored in rb8 in special function register scon. th e baud rate is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 8.20.5 ? baud rate generator and selection ? ). 8.20.3 mode 2 11 bits are transmitted (through txd) or received (through rxd): start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). when data is transmitted, the 9 th data bit (tb8 in scon) can be assigned the value of logic 0 or logic 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. when data is received, the 9 th data bit goes into rb8 in special function register scon, while the stop bit is not saved. the baud rate is programmable to either 1 ? 16 or 1 ? 32 of the cpu clock frequency, as determined by the smod1 bit in pcon. 8.20.4 mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (logic 0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (logic 1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable and is determined by the timer 1 overflow rate or the baud rate generator (described in section 8.20.5 ? baud rate generator and selection ? ). 8.20.5 baud rate generator and selection the p89lpc933/934/935/936 enhanced uart has an independent baud rate generator. the baud rate is determined by a baud-rate preprogrammed into the brgr1 and brgr0 sfrs which together form a 16-bit baud rate divisor value that works in a similar manner as timer 1 but is much more accurate. if the baud rate generator is used, timer 1 can be used for other timing functions. the uart can use either timer 1 or the baud rate generator output (see figure 14 ). note that timer t1 is further divided by 2 if the smod1 bit (pcon.7) is cleared. the independent baud rate generator uses cclk. 8.20.6 framing error framing error is reported in the status regist er (sstat). in addition, if smod0 (pcon.6) is logic 1, framing errors can be made available in scon.7 respectively. if smod0 is logic 0, scon.7 is sm0. it is recommended that sm0 and sm1 (scon.7:6) are set up when smod0 is logic 0. fig 14. baud rate sour ces for uart (modes 1, 3) baud rate modes 1 and 3 sbrgs = 1 sbrgs = 0 smod1 = 0 smod1 = 1 timer 1 overflow (pclk-based) baud rate generator (cclk-based) 002aaa89 7 2
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 40 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.20.7 break detect break detect is reported in the status re gister (sstat). a break is detected when 11 consecutive bits are sensed low. the brea k detect can be used to reset the device and force the device into isp mode. 8.20.8 double buffering the uart has a transmit double buffer that allo ws buffering of the next character to be written to sbuf while the firs t character is being transmitted. double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written be tween the start bit and the stop bit of the previous character. double buffering can be disabled. if disabl ed (dbmod, i.e., sstat.7 = 0), the uart is compatible with the conventio nal 80c51 uart. if enabled, t he uart allows writing to snbuf while the previous data is being shifte d out. double bufferin g is only allowed in modes 1, 2 and 3. when operated in mode 0, double buffering must be disabled (dbmod = 0). 8.20.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) unlike the conventional uart, in double buffering mode, the tx interrupt is generated when the double buffer is ready to receive new data. 8.20.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) if double buffering is disabled tb8 can be written before or after sbuf is written, as long as tb8 is updated some time before that bit is shifted out. tb8 must not be changed until the bit is shifted out, as in dicated by the tx interrupt. if double buffering is enabled, tb8 must be updated before sbuf is written, as tb8 will be double-buffered together with sbuf data.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 41 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.21 i 2 c-bus serial interface the i 2 c-bus uses two wires (sda and scl) to transfer information between devices connected to the bus, and it has the following features: ? bidirectional data transfer between masters and slaves ? multi master bus (no central master) ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus may be used for test and diagnostic purposes. a typical i 2 c-bus configuration is shown in figure 15 . the p89lpc933/934/935/936 device provides a byte-oriented i 2 c-bus interface that supports data transfers up to 400 khz. fig 15. i 2 c-bus configuration other device with i 2 c-bus interface sda scl r p r p other device with i 2 c-bus interface p1.3/sda p1.2/scl p89lpc935 i 2 c-bus 002aab082
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 42 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 16. i 2 c-bus serial interface block diagram internal bus 002aaa89 9 address register comparator shift register 8 i2adr ack bit counter / arbitration and sync logic 8 i2dat timing and control logic serial clock generator cclk interrupt input filter output stage input filter output stage p1.3 p1.3/sda p1.2/scl p1.2 timer 1 overflow control registers and scl duty cycle registers i2con i2sclh i2scll 8 status decoder status bus status register 8 i2stat
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 43 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.22 spi the p89lpc933/934/935/936 provides anot her high-speed serial communication interface?the spi interface. spi is a full-duplex, high-speed, synchronous communication bus with two operation modes : master mode and slave mode. up to 3 mbit/s can be supported in master mode or up to 2 mbit/s in slave mode. it has a transfer completion flag and wr ite collision flag protection. the spi interface has four pins: spiclk, mosi, miso and ss : ? spiclk, mosi and miso are typically ti ed together between two or more spi devices. data flows from master to slave on mosi (master out slave in) pin and flows from slave to master on miso (master in sl ave out) pin. the spic lk signal is output in the master mode and is input in the slav e mode. if the spi system is disabled, i.e., spen (spctl.6) = 0 (res et value), these pins are co nfigured for port functions. ? ss is the optional slave select pin. in a ty pical configuration, an spi master asserts one of its port pins to select one spi devi ce as the current slav e. an spi slave device uses its ss pin to determine whether it is selected. typical connections are shown in figure 18 through figure 20 . fig 17. spi block diagram 002aaa900 cpu clock divider by 4, 16, 64, 128 select clock logic spi control register read data buffer 8-bit shift register spi control spi status register spr1 spif wcol spr0 spi clock (master) pin control logic s m s m m s miso p2.3 mosi p2.2 spiclk p2.5 ss p2.4 spi interrupt request internal data bus ssig spen spen mstr dord mstr cpha cpol spr1 spr0 mstr spen clock
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 44 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.22.1 typical spi configurations fig 18. spi single master single slave configuration fig 19. spi dual device configuration, where either can be a master or a slave 002aaa90 1 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port miso mosi spiclk ss 002aaa90 2 master slave 8-bit shift register spi clock generator spi clock generator 8-bit shift register miso mosi spiclk miso mosi spiclk ss ss
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 45 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 20. spi single master multiple slaves configuration 002aaa90 3 master slave 8-bit shift register spi clock generator 8-bit shift register miso mosi spiclk port port miso mosi spiclk ss slave 8-bit shift register miso mosi spiclk ss
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 46 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.23 analog comparators two analog comparators are provided on the p89lpc933/934/935/936. input and output options allow use of the comparators in a num ber of different configurations. comparator operation is such that the output is a logic 1 (w hich may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). otherwise the output is a zero. each comparator may be configured to cause an interrupt when the output value changes. the overall connections to both comparators are shown in figure 21 . the comparators function to v dd =2.4v. when each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. the corresponding comparator interrupt should not be enabled during that time, and th e comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. when a comparator is disabled the comparator?s output, con, goes high. if the comparator output was low and then is disabled, the resulting transition of the comparator output from a lo w to high state will set the co mparator flag, cmfn. this will cause an interrupt if the comparator interrupt is enabled. the user should therefore disable the comparator interrupt prior to disabling the comparator. additionally, the user should clear the comparator flag, cmfn, after disabling the comparator. 8.23.1 internal reference voltage an internal reference voltage generator may supply a default reference when a single comparator input pin is used. the value of the internal reference voltage, referred to as v ref(bg) , is 1.23 v 10 %. fig 21. comparator input and output connections comparator 1 cp1 cn1 (p0.4) cin1a (p0.3) cin1b (p0.5) cmpref v ref(bg) oe1 change detect co1 cmf1 interrupt 002aaa904 cmp1 (p0.6) ec change detect cmf2 comparator 2 oe2 co2 cmp2 (p0.0) cp2 cn2 (p0.2) cin2a (p0.1) cin2b
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 47 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.23.2 comparator interrupt each comparator has an interrupt flag contained in its configuration register. this flag is set whenever the comparator output changes st ate. the flag may be polled by software or may be used to generate an interrupt. the two comparators use one common interrupt vector. if both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determi ne which comparator caused the interrupt. 8.23.3 comparators and power reduction modes either or both comparators may remain enabled when power-down or idle mode is activated, but both comparators are disabled automatically in total power-down mode. if a comparator interrupt is enabled (except in total power-down mode), a change of the comparator output state will generate an in terrupt and wa ke-up the processor. if the comparator output to a pin is enabled, the pin should be conf igured in the push-pull mode in order to obtain fast switch ing times while in power-down mo de. the reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. comparators consume power in power-down and idle modes, as well as in the normal operating mode. this fact sh ould be taken into account when system power consumption is an issue. to minimize power consumption, the user can disable the comparators via pcona.5, or put the device in total power-down mode. 8.24 keypad interrupt the keypad interrupt (kbi) function is intended primarily to allow a single interrupt to be generated when port 0 is equal to or not equal to a certain pattern. this function can be used for bus address recognition or keypad recognition. the user can configure the port via sfrs for different tasks. the keypad interrupt mask r egister (kbmask) is used to define which input pins connected to port 0 can trigger the interrupt. the keypad pattern register (kbpatn) is used to define a pattern that is compared to the value of port 0. the keypad interrupt flag (kbif) in the keypad interrup t control register (kbcon) is set when the condition is matched while the keypad interrupt function is active. an interrup t will be generated if enabled. the patn_sel bit in the keypad inte rrupt control register (kbcon) is used to define equal or not-equal for the comparison. in order to use the keypad interrupt as an original kbi function like in 87lpc76x series, the user needs to set kbpatn = 0ffh and patn_sel = 1 (not equal), then any key connected to port 0 which is enabled by th e kbmask register will caus e the hardware to set kbif and generate an interrupt if it has been enabled. the interrupt may be used to wake-up the cpu from id le or power-down modes. this feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. in order to set the flag and cause an interrupt, the pattern on port 0 must be held longer than six cclks.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 48 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.25 watchdog timer the watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching it s terminal count. it consists of a programmable 12-bit prescaler, and an 8-bit down counter. the down counter is decremented by a tap taken from the prescaler. the clock source for the prescaler is either the pclk or the nominal 400 khz watchdog oscillator. the watchdog timer can only be reset by a power-on reset. when the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. figure 22 shows the watchdog timer in watchdog mode. feeding the watchdog requires a two-byte sequence. if pclk is selected as the watchdog clock and the cpu is powered-down, the watchdog is disabled. the watchdog timer has a time-out period that ranges from a few s to a few seconds. please refer to the p89lpc933/934/935/936 user manual for more details. 8.26 additional features 8.26.1 software reset the srst bit in auxr1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. care should be taken when writing to auxr1 to avoid accidental software resets. 8.26.2 dual data pointers the dual data pointers (dptr) provides tw o different data poin ters to specify the address used with certain instructions. the d ps bit in the auxr1 register selects one of the two data pointers. bit 2 of auxr1 is pe rmanently wired as a logic 0 so that the dps bit may be toggled (thereby switching data pointers) simply by incrementing the auxr1 register, without the possibilit y of inadvertently altering other bits in the register. (1) watchdog reset can also be caused by an in valid feed sequence, or by writing to wd con not immediately followed by a feed sequence. fig 22. watchdog timer in watchdog mode (wdte = 1) pre2 pre1 pre0 - - wdrun wdtof wdclk wdcon (a7h) shadow register prescaler 002aaa90 5 8-bit down counter wdl (c1h) watchdog oscillator pclk 32 mov wfeed1, #0a5h mov wfeed2, #05ah reset (1)
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 49 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.27 data eeprom (p89lpc935/936) the p89lpc935/936 has 512 bytes of on -chip data eeprom. the data eeprom is sfr based, byte readable, byte writable, and erasable (via row fill and sector fill). the user can read, write and fill the memory via sfrs and one interrupt. this data eeprom provides 100,000 minimum erase/ program cycles for each byte. ? byte mode: in this mode, data can be read and written one byte at a time. ? row fill: in this mode, the addressed row (64 byt es) is filled with a single value. the entire row can be erased by writing 00h. ? sector fill: in this mode, all 512 bytes are filled with a single value. the entire sector can be erased by writing 00h. after the operation finishes, the hardware will set the eeif bit, which if enabled will generate an interrupt. the flag is cleared by software. 8.28 flash program memory 8.28.1 general description the p89lpc933/934/935/936 flash memory prov ides in-circuit electrical erasure and programming. the flash can be erased, read, and written as bytes. the sector and page erase functions can erase any flash sector (1 kb or 2 kb depending on the device) or page (64 bytes). the chip erase operation will er ase the entire pr ogram memory. icp using standard commercial programmers is available. in addition, iap and byte-erase allows code memory to be used for non-vola tile data storage. on-chip erase and write timing generation contribute to a user -friendly programming interface. the p89lpc933/934/935/936 flash reliably stores memory contents even after 100,000 erase and program cycles. the cell is designed to optimize the erase and programming mechanisms. the p89lpc933/934/935/936 uses v dd as the supply voltage to perform the program/erase algorithms. 8.28.2 features ? programming and erase over the full operating voltage range. ? byte erase allows code memory to be used for data storage. ? read/programming/erase using isp/iap/icp. ? internal fixed boot rom, containing low-le vel iap routines available to user code. ? default loader providing isp via the serial port, located in upper end of user program memory. ? boot vector allows user-provided flash loader code to reside anywhere in the flash memory space, providing flexibility to the user. ? any flash program/erase operation in 2 ms. ? programming with industry-standard commercial programmers. ? programmable security for the code in the flash for each sector. ? 100,000 typical erase/program cycles for each byte. ? 10 year minimum data retention.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 50 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.28.3 flash organization the program memory consists of eight 2 kb sectors on the p89lpc936 device, eight 1 kb sectors on the p89lpc934/935 devices, and four 1 kb sectors on the p89lpc933 device. each sector can be further divided into 64-byte pages. in addition to sector erase, page erase, and byte erase, a 64-byte page regist er is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. 8.28.4 using flash as data storage the flash code memory array of this devi ce supports individual byte erasing and programming. any byte in the code memory array may be read using the movc instruction, provided that the sector containing the byte has not been secured (a movc instruction is not allowed to read code memory contents of a secured sector). thus any byte in a non-secured sector may be used for non-volatile data storage. 8.28.5 flash programming and erasing four different methods of erasing or progra mming of the flash are available. the flash may be programmed or erased in the end-user application (iap) under control of the application?s firmware. another option is to use the icp mechanism. this icp system provides for programming through a serial clock - serial data interface. as shipped from the factory, the upper 512 bytes of user code space contains a serial isp routine allowing the device to be programmed in circuit thr ough the serial port. the flash may also be programmed or erased using a commercially available eprom programmer which supports this device. this device does not pr ovide for direct verifica tion of code memory contents. instead, this device provides a 32-bit crc result on either a sector or the entire user code space. 8.28.6 in-circuit programming icp is performed without removing the microcont roller from the system. the icp facility consists of internal hardw are resources to facilitate remote programming of the p89lpc933/934/935/9 36 through a two-wire se rial interface. the philips icp facility has made icp in an embedded application?using commercially available programmers?possible with a minimum of addi tional expense in components and circuit board area. the icp function uses five pins. only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. additional details may be found in the p89lpc933/934/935/936 user manual . 8.28.7 in-application programming iap is performed in the application under the control of the microcontroller?s firmware. the iap facility consists of inter nal hardware resource s to facilitate programming and erasing. the philips iap has made iap in an embedde d application possible without additional components. two methods are available to accomplish iap. a set of predefined iap functions are provided in a boot rom and can be called through a common interface, pgm_mtp. several iap calls are available fo r use by an application program to permit selective erasing and programming of flash se ctors, pages, security bits, configuration bytes, and device id. these functions are selected by setting up the microcontroller?s registers before making a call to pgm_mtp at ff03h. the boot rom occupies the program memory space at the top of the address space from ff00h to ffefh, thereby not conflicting with the user program memory space.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 51 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core in addition, iap operations can be accomplish ed through the use of f our sfrs consisting of a control/status register, a data register, and two address register s. additional details may be found in the p89lpc933/934/935/936 user manual . 8.28.8 isp isp is performed without remo ving the microcontroller from the system. the isp facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the p89lpc 933/934/935/ 936 through the serial port. this firmware is provided by philips an d embedded within each p89lpc933/934/935/936 device. the philips isp facility has made isp in an embedded applic ation possible with a minimum of additional expense in component s and circuit board area. the isp function uses five pins (v dd , v ss , txd, rxd, and rst ). only a small connector needs to be available to interface your application to an external circuit in order to use this feature. 8.28.9 power-on reset code execution the p89lpc933/934/935/936 cont ains two special flash elem ents: the boot vector and the boot status bit. following reset, the p89lpc933/934/935/936 examines the contents of the boot status bit. if the boot status bi t is set to zero, power-up execution starts at location 0000h, which is the normal start add ress of the user?s application code. when the boot status bit is set to a value other than zero, the contents of the boot vector are used as the high byte of the execution address and the low byte is set to 00h. ta b l e 9 shows the factory default boot ve ctor settings for these devices. remark: these settings are different than the original p89lpc932. tools designed to support the p89lpc933/934/935/936 should be used to program this device, such as flash magic version 1.98, or later. a factory-provided boot loader is preprogrammed into the address space indicated and uses the indicated boot loader entry point to perform isp functions. this code can be erased by the user. remark: users who wish to use this loader should take precautions to avoid erasing the sector that contains this boot loader. inst ead, the page erase function can be used to erase the pages located in this sector which are not used by the boot loader. a custom boot loader can be written with the boot vector set to the custom boot loader, if desired. table 9. default boot vector values and isp entry points device default boot vector default boot loader entry point default boot loader code range boot sector range p89lpc933 0fh 0f00h 0e00h to 0fffh 0c00h to 0fffh p89lpc934 1fh 1f00h 1e00h to 1fffh 1c00h to 1fffh p89lpc935 1fh 1f00h 1e00h to 1fffh 1c00h to 1fffh p89lpc936 3fh 3f00h 3e00h to 3fffh 3c00h to 3fffh
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 52 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 8.28.10 hardware activation of the boot loader the boot loader can also be executed by forcing the device into isp mode during a power-on sequence (see the p89lpc933/934/935/936 user manual for specific information). this has the same effect as having a non-zero status byte. this allows an application to be built that will normally execute user code but can be man ually forced into isp operation. if the factory def ault setting for the boot vector is changed, it will no longer point to the factory preprogrammed isp boot loader code. after programming the flash, the status byte should be programmed to zero in order to allow execution of the user?s application code beginning at address 0000h. 8.29 user configuration bytes some user-configurable features of the p89lpc933/934/935/936 must be defined at power-up and therefore cannot be set by the program after start of execution. these features are configured through the use of the flash byte ucfg1. please see the p89lpc933/934/935/936 user manual for additional details. 8.30 user sector security bytes there are eight user sector security bytes on the p89lpc933/934/935/936 device. each byte corresponds to one sector. pl ease see the p89lpc933/934/935/936 user manual for additional details. 9. a/d converter 9.1 general description the p89lpc935/936 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. the p89lpc933/934 have a single 8-bit, 4-channel multiplexed analog-to-digital converter and an additional dac module. a block diagram of the a/d converter is shown in figure 23 . each a/d consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. the control logic in combination with the sar drives a digital-to-analog converter which prov ides the other input to the comparator. the output of the comparator is fed to the sar. 9.2 features and benefits ? two (p89lpc935/936) 8-bit, 4-channel mult iplexed input, successive approximation a/d converters with common control l ogic (one a/d on the p89lpc933/934). ? four result registers for each a/d. ? six operating modes: ? fixed channel, single conversion mode. ? fixed channel, continuous conversion mode. ? auto scan, single conversion mode. ? auto scan, continuous conversion mode. ? dual channel, continuous conversion mode. ? single step mode. ? four conversion start modes: ? timer triggered start.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 53 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core ? start immediately. ? edge triggered. ? dual start immediately (p89lpc935/936). ? 8-bit conversion time of 3.9 s at an a/d clock of 3.3 mhz. ? interrupt or polled operation. ? boundary limits interrupt. ? dac output to a port pin with high output impedance. ? clock divider. ? power-down mode. 9.3 block diagram 9.4 a/d operating modes 9.4.1 fixed channel, single conversion mode a single input channel can be selected fo r conversion. a single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. an interrupt, if enabled, will be generated af ter the conversion completes. fig 23. adc block diagram + ? comp dac1 sar 8 input mux control logic + ? comp dac0 sar 8 input mux cclk 002aab08 0
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 54 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 9.4.2 fixed channel, continuous conversion mode a single input channel can be selected for continuous conversion. the results of the conversions will be sequentially placed in the four result registers. an interrupt, if enabled, will be generated after every four conversions. additional conversion results will again cycle through the four result registers, ov erwriting the previous results. continuous conversions continue until terminated by the user. 9.4.3 auto scan, single conversion mode any combination of the four input channels can be selected for conversion. a single conversion of each selected in put will be performed and the re sult placed in the result register which corresponds to th e selected input channel. an in terrupt, if en abled, will be generated after all selected channels have be en converted. if only a single channel is selected this is equivalent to si ngle channel, single conversion mode. 9.4.4 auto scan, continuous conversion mode any combination of the four input channels ca n be selected for conversion. a conversion of each selected input will be performed and th e result placed in the result register which corresponds to the sele cted input channel. an interrupt, if enabled, will be generated after all selected channels have been converted. the process will re peat starting with the first selected channel. additional conversion results will again cycle through the four result registers, overwriting the previous result s. continuous conversi ons continue until terminated by the user. 9.4.5 dual channel, continuous conversion mode this is a variation of the auto scan contin uous conversion mode where conversion occurs on two user-selectable inputs. the result of t he conversion of the first channel is placed in result register, adxdat0. the result of the c onversion of the second channel is placed in result register, adxdat1. the first channel is again converted and its result stored in adxdat2. the second channel is again conver ted and its result placed in adxdat3. an interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). 9.4.6 single step mode this special mode allows ?s ingle-stepping? in an auto scan conversion mode. any combination of the four input channels can be selected for conversion. after each channel is converted, an interrupt is generated, if enabled, and the a/d waits for the next start condition. may be used with any of the start modes. 9.5 conversion start modes 9.5.1 timer triggered start an a/d conversion is started by the overflow of timer 0. once a conversion has started, additional timer 0 triggers are ignored unt il the conversion has completed. the timer triggered start mode is available in all a/d operating modes. 9.5.2 start immediately programming this mode immediately starts a conv ersion. this start mode is available in all a/d operating modes.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 55 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 9.5.3 edge triggered an a/d conversion is started by rising or falling edge of p1.4. once a conversion has started, additional edge triggers are ignored until the conversion has completed. the edge triggered start mode is available in all a/d operating modes. 9.5.4 dual start immediately (p89lpc935/936) programming this mode starts a synchronized conversion of both a/d converters. this start mode is available in all a/d operating modes. both a/d converters must be in the same operating mode. in the continuous conv ersion modes, both a/d converters must select an identical number of channels. any trigger of either a/d will st art a simultaneous conversion of both a/ds. 9.6 boundary limits interrupt each of the a/d converters has both a high and low boundary limit register. after the four msbs have been converted, these four bits are compared with the four msbs of the boundary high and low registers. if the four msbs of the conversion are outside the limit an interrupt will be generated, if enabled. if the conversion re sult is within the limits, the boundary limits will again be compared after a ll 8 bits have been conv erted. an interrupt will be generated, if enabled, if the result is outside th e boundary limits. the boundary limit may be disabled by clearing the boundary limit interrupt enable. 9.7 dac output to a port pin with high output impedance each a/d converter?s dac block can be output to a port pin. in this mode, the adxdat3 register is used to hold the value fed to th e dac. after a value has been written to the dac (written to adxdat3), the dac output will appear on the channel 3 pin. 9.8 clock divider the a/d converter requires that its internal clock source be in the range of 500 khz to 3.3 mhz to maintain accuracy. a programma ble clock divider that divides the clock from 1 to 8 is provided for this purpose. 9.9 power-down and idle mode in idle mode the a/c converte r, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the a/d interrupt is enabled. in power-down mode or total power-down mode, the a/d does not function. if the a/d is enabled, it will consume power. power ca n be reduced by disabling the a/d.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 56 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 10. limiting values [1] the following applies to table 10 : a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over ambient temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. table 10. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit t amb(bias) bias ambient temperature ? 55 +125 c t stg storage temperature ? 65 +150 c i oh(i/o) high-level output current per input/output pin -20ma i ol(i/o) low-level output current per input/output pin -20ma i i/otot(max) maximum total input/output current - 100 ma v xtal crystal voltage on xtal1, xtal2 pin to v ss -v dd + 0.5 v v n voltage on any other pin except xtal1, xtal2 to v ss ? 0.5 +5.5 v p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 57 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 11. static characteristics table 11. static characteristics v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. symbol parameter conditions min typ [1] max unit i dd(oper) operating supply current v dd = 3.6 v; f osc =12mhz [2] -1118ma v dd = 3.6 v; f osc =18mhz [2] -1423ma i dd(idle) idle mode supply current v dd = 3.6 v; f osc =12mhz [2] -3.255ma v dd = 3.6 v; f osc =18mhz [2] -57ma i dd(pd) power-down mode supply current v dd = 3.6 v; voltage comparators powered down [2] -5580 a i dd(tpd) total power-down mode supply current all devices except p89lpc933hdh; v dd =3.6v [3] -15 a p89lpc933hdh only; v dd =3.6v [3] --25 a (dv/dt) r rise rate of v dd --2mv/ s (dv/dt) f fall rate of v dd --50mv/ s v por power-on reset voltage - - 0.5 v v ddr data retention supply voltage 1.5 - - v v th(hl) high-low threshold voltage except scl, sda 0.22v dd 0.4v dd -v v il low-level input voltage scl, sda only ? 0.5 - 0.3v dd v v th(lh) low-high threshold voltage except scl, sda - 0.6v dd 0.7v dd v v ih high-level input voltage scl, sda only 0.7v dd -5.5v v hys hysteresis voltage port 1 - 0.2v dd -v v ol low-level output voltage i ol =20ma; v dd = 2.4 v to 3.6 v all ports, all modes except high-z [4] -0.61.0v i ol = 3.2 ma; v dd =2.4v to 3.6 v all ports, all modes except high-z -0.20.3v v oh high-level output voltage i oh = ? 20 a; v dd = 2.4 v to 3.6 v; all ports, quasi-bidirectional mode v dd ? 0.3 v dd ? 0.2 - v i oh = ? 3.2 ma; v dd = 2.4 v to 3.6 v; all ports, push-pull mode v dd ? 0.7 v dd ? 0.4 - v i oh = ? 10 ma; v dd =3.6v; all ports, push-pull mode -3.2-v v xtal crystal voltage on xtal1, xtal2 pins; with respect to v ss ? 0.5 - +4.0 v v n voltage on any other pin except xtal1, xtal2, v dd ; with respect to v ss [5] ? 0.5 - +5.5 v c iss input capacitance [6] --15pf
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 58 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] typical ratings are not guaranteed. the va lues listed are at room temperature, 3 v. [2] the i dd(oper) , i dd(idle) , and i dd(pd) specifications are measured using an external clock with the followi ng functions disabled: comparators, real-time clock, and watchdog timer. [3] the i dd(tpd) specification is measured using an exte rnal clock with the follow ing functions disabled: comp arators, real-time clock, brownout detect, and watchdog timer. [4] see section 10 ? limiting values ? for steady state (non-transient) limits on i ol or i oh . if i ol /i oh exceeds the test condition, v ol /v oh may exceed the related specification. [5] this specification can be applied to pins which have a/d input or analog comparator input functions when the pin is not bein g used for those analog functions. when the pin is being used as an analog i nput pin, the maximum voltage on the pin must be limited to 4. 0 v with respect to v ss . [6] pin capacitance is characterized but not tested. [7] measured with port in quasi-bidirectional mode. [8] measured with port in high-impedance mode. [9] port pins source a transition current when used in quasi-bidire ctional mode and externally driven from logic 1 to logic 0. t his current is highest when v i is approximately 2 v. i il low-level input current v i =0.4v [7] -- ? 80 a i li input leakage current v i =v il ,v ih or v th(hl) [8] -- 10 a i thl high-low transition current all ports; v i =1.5v at v dd =3.6v [9] ? 30 - ? 450 a r rst_n(int) internal pull-up resistance on pin rst 10 - 30 k v bo brownout trip voltage 2.4 v < v dd < 3.6 v; with bov = 1, bopd = 0 2.40 - 2.70 v v ref(bg) band gap reference voltage 1.11 1.23 1.34 v tc bg band gap temperature coefficient -1020ppm/ c table 11. static characteristics ?continued v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. symbol parameter conditions min typ [1] max unit
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 59 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 11.1 i oh as a function of v oh a. t amb = 25 c; v dd = 3.6 v; push-pull mode b. t amb = 25 c; v dd = 2.6 v; push-pull mode fig 24. i oh as a function of v oh (typical values) 002aab098 0 10 20 30 40 01234 v oh i oh 002aab099 0 5 10 15 20 25 0123 v oh i oh
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 60 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 12. dynamic characteristics table 12. dynamic characteristics (12 mhz) v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =12mhz unit min max min max f osc(rc) internal rc oscillator frequency 7.189 7.557 7.189 7.557 mhz f osc(wd) internal watch dog oscillator frequency 320 520 320 520 khz f osc oscillator frequency 0 12 - - mhz t cy(clk) clock cycle time see figure 27 83 - - - ns f clklp low-power select clock frequency 08--mhz glitch filter t gr glitch rejection time p1.5/rst pin - 50 - 50 ns any pin except p1.5/rst - 15 - 15 ns t sa signal acceptance time p1.5/rst pin 125 - 125 - ns any pin except p1.5/rst 50 - 50 - ns external clock t chcx clock high time see figure 27 33 t cy(clk) ? t clcx 33 - ns t clcx clock low time see figure 27 33 t cy(clk) ? t chcx 33 - ns t clch clock rise time see figure 27 -8-8ns t chcl clock fall time see figure 27 -8-8ns shift register (uart mode 0) t xlxl serial port clo ck cycle time see figure 25 16t cy(clk) - 1333 - ns t qvxh output data set-up to clock rising edge time see figure 25 13t cy(clk) - 1083 - ns t xhqx output data hold after clock rising edge time see figure 25 -t cy(clk) +20 - 103 ns t xhdx input data hold after clock rising edge time see figure 25 -0-0ns t xhdv input data valid to clock rising edge time see figure 25 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk ? 6 02.0mhz master - cclk ? 4 -3.0mhz t spicyc spi cycle time see figure 26 , 28 , 29 , 30 slave 6 ? cclk -500-ns master 4 ? cclk -333-ns t spilead spi enable lead time see figure 29 , 30 slave 250 - 250 - ns
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 61 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over ambient te mperature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spilag spi enable lag time see figure 29 , 30 slave 250 - 250 - ns t spiclkh spiclk high time see figure 26 , 28 , 29 , 30 master 2 ? cclk -165-ns slave 3 ? cclk -250-ns t spiclkl spiclk low time see figure 26 , 28 , 29 , 30 master 2 ? cclk -165-ns slave 3 ? cclk -250-ns t spidsu spi data set-up time see figure 26 , 28 , 29 , 30 master or slave 100 - 100 - ns t spidh spi data hold time see figure 26 , 28 , 29 , 30 master or slave 100 - 100 - ns t spia spi access time see figure 29 , 30 slave 0 120 0 120 ns t spidis spi disable time see figure 29 , 30 slave 0 240 - 240 ns t spidv spi enable to output data valid time see figure 26 , 28 , 29 , 30 slave - 240 - 240 ns master - 167 - 167 ns t spioh spi output data hold time see figure 26 , 28 , 29 , 30 0-0-ns t spir spi rise time see figure 26 , 28 , 29 , 30 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 26 , 28 , 29 , 30 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 12. dynamic characteristics (12 mhz) ?continued v dd = 2.4 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =12mhz unit min max min max
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 62 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core table 13. dynamic characteristics (18 mhz) v dd = 3.0 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max f osc(rc) internal rc oscillator frequency 7.189 7.557 7.189 7.557 mhz f osc(wd) internal watchdog oscillator frequency 320 520 320 520 khz f osc oscillator frequency 0 18 - - mhz t cy(clk) clock cycle see figure 27 55 - - - ns f clklp low-power select clock frequency 08--mhz glitch filter t gr glitch rejection time p1.5/rst pin - 50 - 50 ns any pin except p1.5/rst - 15 - 15 ns t sa signal acceptance time p1.5/rst pin 125 - 125 - ns any pin except p1.5/rst 50 - 50 - ns external clock t chcx clock high time see figure 27 22 t cy(clk) ? t clcx 22 - ns t clcx clock low time see figure 27 22 t cy(clk) ? t chcx 22 - ns t clch clock rise time see figure 27 -5-5ns t chcl clock fall time see figure 27 -5-5ns shift register (uart mode 0) t xlxl serial port clock cycle time see figure 25 16t cy(clk) -888-ns t qvxh output data set-up to clock rising edge time see figure 25 13t cy(clk) -722-ns t xhqx output data hold after clock rising edge time see figure 25 -t cy(clk) + 20 - 75 ns t xhdx input data hold after clock rising edge time see figure 25 -0-0ns t xhdv input data valid to clock rising edge time see figure 25 150 - 150 - ns spi interface f spi spi operating frequency slave 0 cclk ? 6 03.0mhz master - cclk ? 4 -4.5mhz t spicyc spi cycle time see figure 26 , 28 , 29 , 30 slave 6 ? cclk -333-ns master 4 ? cclk -222-ns t spilead spi enable lead time see figure 29 , 30 slave 250 - 250 - ns t spilag spi enable lag time see figure 29 , 30 slave 250 - 250 - ns
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 63 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core [1] parameters are valid over ambient te mperature range unless otherwise specified. [2] parts are tested to 2 mhz, but are guaranteed to operate down to 0 hz. t spiclkh spiclk high time see figure 26 , 28 , 29 , 30 master 2 ? cclk -111-ns slave 3 ? cclk -167-ns t spiclkl spiclk low time see figure 26 , 28 , 29 , 30 master 2 ? cclk -111-ns slave 3 ? cclk -167-ns t spidsu spi data set-up time see figure 26 , 28 , 29 , 30 master or slave 100 - 100 - ns t spidh spi data hold time see figure 26 , 28 , 29 , 30 master or slave 100 - 100 - ns t spia spi access time see figure 29 , 30 slave 0 80 0 80 ns t spidis spi disable time see figure 29 , 30 slave 0 160 - 160 ns t spidv spi enable to output data valid time see figure 26 , 28 , 29 , 30 slave - 160 - 160 ns master - 111 - 111 ns t spioh spi output data hold time see figure 26 , 28 , 29 , 30 0-0-ns t spir spi rise time see figure 26 , 28 , 29 , 30 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns t spif spi fall time see figure 26 , 28 , 29 , 30 spi outputs (spiclk, mosi, miso) - 100 - 100 ns spi inputs (spiclk, mosi, miso, ss ) - 2000 - 2000 ns table 13. dynamic characteristics (18 mhz) ?continued v dd = 3.0 v to 3.6 v unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. [1] [2] symbol parameter conditions variable clock f osc =18mhz unit min max min max
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 64 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 12.1 waveforms fig 25. shift register mode timing 0 1234567 valid valid valid valid valid valid valid valid t xlxl 002aaa90 6 set ti set ri t xhqx t qvxh t xhdv t xhdx clock output data write to sbuf input data clear ri fig 26. spi master timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa908 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 27. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa90 7
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 65 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 28. spi master timing (cpha = 1) t spicyc t spiclkl t spiclkl t spiclkh t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa909 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 29. spi slave timing (cpha = 0) t spicyc t spiclkh t spiclkh t spiclkl t spiclkl t spilead t spilag t spidsu t spidh t spidh t spidsu t spidsu t spif t spia t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spioh t spidv t spir t spir t spif t spif ss spiclk (cpol = 0) (input) 002aaa910 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 66 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 12.2 isp entry mode fig 30. spi slave timing (cpha = 1) 002aaa911 t spicyc t spiclkh t spiclkh t spiclkl t spilead t spiclkl t spilag t spidsu t spidsu t spidh t spidh t spif t spir t spir t spia t spioh t spioh t spioh t spidis slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spidv t spidv t spir t spif t spif ss spiclk (cpol = 0) (input) spiclk (cpol = 1) (input) miso (output) mosi (input) table 14. dynamic characteristics, isp entry mode v dd = 2.4 v to 3.6 v, unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. symbol parameter conditions min typ max unit t vr rst delay from v dd active time 50 - - s t rh rst high time 1 - 32 s t rl rst low time 1 - - s fig 31. isp entry timing 002aaa91 2 v dd rst t rl t vr t rh
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 67 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 13. other characteristics 13.1 comparator electr ical characteristics [1] this parameter is characterized, but not tested in production. table 15. comparator electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. symbol parameter conditions min typ max unit v io input offset voltage - - 20 mv v ic common-mode input voltage 0 - v dd ? 0.3 v cmrr common-mode rejection ratio [1] -- ? 50 db t res(tot) total response time - 250 500 ns t (ce-ov) chip enable to output valid time - - 10 s i li input leakage current 0 < v i p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 68 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 13.2 adc electrical characteristics table 16. adc electrical characteristics v dd = 2.4 v to 3.6 v, unless otherwise specified. t amb = ? 40 cto+85 c for industrial, ? 40 cto+125 c for extended, unless otherwise specified. all limits valid for an external source impedance of less than 10 k . symbol parameter conditions min typ max unit v ia analog input voltage v ss ? 0.2 - v dd +0.2 v c iss input capacitance - - 15 pf e d differential linearity error - - 1lsb e l(adj) integral non-linearity - - 1lsb e o offset error - - 2lsb e g gain error - - 1% e u(tot) total unadjusted error - - 2lsb m ctc channel-to-channel matching - - 1lsb ct(port) crosstalk between port inputs 0 khz to 100 khz - - ? 60 db sr in input slew rate - - 100 v/ms t cy(adc) adc clock cycle time 111 - 2000 ns t adc adc conversion time a/d enabled - - 13t cy(adc) ns
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 69 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 14. package outline fig 32. package outline sot261-2 (plcc28) references outline version european projection issue date iec jedec jeita note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot261-2 112e08 ms-018 edr-7319 19 25 28 1 4 511 18 12 26 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 k x y e e b d h e h v m b d z d a z e e v m a 0 5 10 mm scale 99-12-27 01-11-15 pin 1 index plcc28: plastic leaded chip carrier; 28 leads sot261- 2 unit mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 1.27 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) 11.58 11.43 12.57 12.32 2.16 0.81 0.66 1.22 1.07 0.180 0.165 0.02 0.12 0.25 0.01 0.05 0.085 0.007 0.004 0.007 1.44 1.02 0.057 0.040 0.456 0.450 11.58 11.43 0.456 0.450 0.495 0.485 12.57 12.32 0.495 0.485 10.92 9.91 0.43 0.39 10.92 9.91 0.43 0.39 0.085 0.032 0.026 0.048 0.042 e e inches d e a a 1 min. a 4 max. b p ey w v d (1) e (1) h d h e z d (1) max. z e (1) max. b 1 k a 3 l p e d e e
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 70 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 33. package outline sot361-1 (tssop28) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 114 28 15 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale t ssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361 -1 a max. 1.1
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 71 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core fig 34. package outline sot788-1 (hvqfn28) 0.65 1 a 1 e h bc unit y e references outline version european projection issue date iec jedec jeita mm 6.1 5.9 6.1 5.9 d h 4.25 3.95 y 1 4.25 3.95 e 1 3.9 e 2 3.9 0.35 0.25 0.05 0.00 0.2 0.05 0.1 dimensions (mm are the original dimensions) sot788-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot788 -1 h vqfn28: plastic thermal enhanced very thin quad flat package; no leads; 2 8 terminals; body 6 x 6 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 814 28 22 21 15 7 1 x d e c b a e 2 02-10-22 terminal 1 index area terminal 1 index area a c c b v m w m note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) e (1)
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 72 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 15. abbreviations table 17. acronym list acronym description a/d analog to digital cpu central processing unit dac digital to analog converter eprom erasable programmable read-only memory eeprom electrically erasable programmable read-only memory emi electro-magnetic interference led light emitting diode pwm pulse width modulator ram random access memory rc resistance-capacitance rtc real-time clock sar successive approximation register sfr special function register spi serial peripheral interface uart universal asynchronous receiver/transmitter
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 73 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 16. revision history table 18. revision history document id release date data sheet status change notice supersedes p89lpc933_934_ 935_936 v.8 20110112 product data sheet - p89lpc933_934_ 935_936 v.7 modifications: ? table 10 ? limiting values ? : changed v n max to 5.5 v. ? ta b l e 11 ? static characteristics ? : added v por . ? table 16 ? adc electrical characteristics ? : corrected v ia max. ? section 8.16 ? reset ? : added sentence ?when this pin functions as a reset input....? p89lpc933_934_ 935_936 v.7 20081126 product data sheet - p89lpc933_934_ 935_936 v.6 p89lpc933_934_ 935_936 v.6 20050620 product data sheet - p89lpc933_934_ 935_936 v.5 p89lpc933_934_ 935_936 v.5 20041103 product data sheet - p89lpc933_934_ 935 v.4 p89lpc933_934_ 935 v.4 20040209 objective data - p89lpc933_934_ 935 v.3
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 74 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 75 of 77 nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
p89lpc933_934_935_936 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights rese rved. product data sheet rev. 8 ? 12 january 2011 76 of 77 continued >> nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 additional features . . . . . . . . . . . . . . . . . . . . . . 2 3 product comparison overview . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 functional description . . . . . . . . . . . . . . . . . . 12 8.1 special function registers . . . . . . . . . . . . . . . . 12 8.2 enhanced cpu . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.1 clock definitions . . . . . . . . . . . . . . . . . . . . . . . 24 8.3.2 cpu clock (oscclk). . . . . . . . . . . . . . . . . . . 24 8.3.3 low speed oscillator option . . . . . . . . . . . . . . 24 8.3.4 medium speed oscillator option . . . . . . . . . . . 24 8.3.5 high speed oscillator option . . . . . . . . . . . . . . 24 8.3.6 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 on-chip rc oscillator option . . . . . . . . . . . . . . 25 8.5 watchdog oscillator option . . . . . . . . . . . . . . . 25 8.6 external clock input option . . . . . . . . . . . . . . . 25 8.7 cclk wake-up delay . . . . . . . . . . . . . . . . . . . 27 8.8 cclk modification: divm register . . . . . . . . . 27 8.9 low power select . . . . . . . . . . . . . . . . . . . . . . 27 8.10 memory organization . . . . . . . . . . . . . . . . . . . 27 8.11 data ram arrangement . . . . . . . . . . . . . . . . . 28 8.12 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.1 external interrupt inputs . . . . . . . . . . . . . . . . . 28 8.13 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.13.1 port configurations . . . . . . . . . . . . . . . . . . . . . 30 8.13.1.1 quasi-bidirectional outp ut configuration . . . . . 30 8.13.1.2 open-drain output configuration . . . . . . . . . . . 30 8.13.1.3 input-only configuration . . . . . . . . . . . . . . . . . 31 8.13.1.4 push-pull output configuration . . . . . . . . . . . . 31 8.13.2 port 0 analog functions . . . . . . . . . . . . . . . . . . 31 8.13.3 additional port features. . . . . . . . . . . . . . . . . . 31 8.14 power monitoring functions . . . . . . . . . . . . . . 31 8.14.1 brownout detection . . . . . . . . . . . . . . . . . . . . . 32 8.14.2 power-on detection. . . . . . . . . . . . . . . . . . . . . 32 8.15 power reduction modes . . . . . . . . . . . . . . . . . 32 8.15.1 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.15.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 32 8.15.3 total power-down mode . . . . . . . . . . . . . . . . 33 8.16 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.16.1 reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.17 timers/counters 0 and 1 . . . . . . . . . . . . . . . . 34 8.17.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17.5 mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.17.6 timer overflow toggle output . . . . . . . . . . . . . 34 8.18 rtc/system timer . . . . . . . . . . . . . . . . . . . . . 34 8.19 ccu (p89lpc935/936) . . . . . . . . . . . . . . . . . 35 8.19.1 ccu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.19.2 ccuclk prescaling. . . . . . . . . . . . . . . . . . . . 35 8.19.3 basic timer operation . . . . . . . . . . . . . . . . . . . 35 8.19.4 output compare . . . . . . . . . . . . . . . . . . . . . . . 35 8.19.5 input capture . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.19.6 pwm operation . . . . . . . . . . . . . . . . . . . . . . . 36 8.19.7 alternating output mode. . . . . . . . . . . . . . . . . 37 8.19.8 pll operation. . . . . . . . . . . . . . . . . . . . . . . . . 37 8.19.9 ccu interrupts . . . . . . . . . . . . . . . . . . . . . . . . 38 8.20 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.20.1 mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.20.2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.20.3 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.20.4 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.20.5 baud rate generator and selection. . . . . . . . . 39 8.20.6 framing error . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.20.7 break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.20.8 double buffering. . . . . . . . . . . . . . . . . . . . . . . 40 8.20.9 transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . 40 8.20.10 the 9 th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . 40 8.21 i 2 c-bus serial interface. . . . . . . . . . . . . . . . . . 41 8.22 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.22.1 typical spi configurations . . . . . . . . . . . . . . . 44 8.23 analog comparators. . . . . . . . . . . . . . . . . . . . 46 8.23.1 internal reference voltage . . . . . . . . . . . . . . . 46 8.23.2 comparator interrupt . . . . . . . . . . . . . . . . . . . 47 8.23.3 comparators and power reduction modes . . . 47 8.24 keypad interrupt. . . . . . . . . . . . . . . . . . . . . . . 47 8.25 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 48 8.26 additional features . . . . . . . . . . . . . . . . . . . . . 48 8.26.1 software reset . . . . . . . . . . . . . . . . . . . . . . . . 48 8.26.2 dual data pointers . . . . . . . . . . . . . . . . . . . . . 48 8.27 data eeprom (p89lpc935/936) . . . . . . . . . 49 8.28 flash program memory . . . . . . . . . . . . . . . . . 49
nxp semiconductors p89lpc933/934/935/936 8-bit microcontroller with accelerated two-clock 80c51 core ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 12 january 2011 document identifier: p89lpc933_934_935_936 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 8.28.1 general description . . . . . . . . . . . . . . . . . . . . 49 8.28.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.28.3 flash organization . . . . . . . . . . . . . . . . . . . . . 50 8.28.4 using flash as data storage . . . . . . . . . . . . . . 50 8.28.5 flash programming and erasing . . . . . . . . . . . 50 8.28.6 in-circuit programming . . . . . . . . . . . . . . . . . . 50 8.28.7 in-application programming . . . . . . . . . . . . . . 50 8.28.8 isp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.28.9 power-on reset code execution . . . . . . . . . . . 51 8.28.10 hardware activation of the boot loader . . . . . . 52 8.29 user configuration bytes . . . . . . . . . . . . . . . . . 52 8.30 user sector security bytes . . . . . . . . . . . . . . . 52 9 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 general description . . . . . . . . . . . . . . . . . . . . 52 9.2 features and benefits . . . . . . . . . . . . . . . . . . . 52 9.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.4 a/d operating modes . . . . . . . . . . . . . . . . . . . 53 9.4.1 fixed channel, single conversion mode . . . . . 53 9.4.2 fixed channel, contin uous conversion mode . 54 9.4.3 auto scan, single conversion mode . . . . . . . . 54 9.4.4 auto scan, continuous conversion mode . . . . 54 9.4.5 dual channel, continuous conversion mode . . 54 9.4.6 single step mode . . . . . . . . . . . . . . . . . . . . . . 54 9.5 conversion start modes . . . . . . . . . . . . . . . . . 54 9.5.1 timer triggered start . . . . . . . . . . . . . . . . . . . . 54 9.5.2 start immediately . . . . . . . . . . . . . . . . . . . . . . 54 9.5.3 edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 55 9.5.4 dual start immediately (p89lpc935/936) . . . 55 9.6 boundary limits interrupt . . . . . . . . . . . . . . . . . 55 9.7 dac output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.8 clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.9 power-down and idle mode . . . . . . . . . . . . . . 55 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 56 11 static characteristics. . . . . . . . . . . . . . . . . . . . 57 11.1 i oh as a function of v oh . . . . . . . . . . . . . . . . . 59 12 dynamic characteristics . . . . . . . . . . . . . . . . . 60 12.1 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.2 isp entry mode . . . . . . . . . . . . . . . . . . . . . . . . 66 13 other characteristics . . . . . . . . . . . . . . . . . . . . 67 13.1 comparator electrical characteristics . . . . . . . 67 13.2 adc electrical characteristics . . . . . . . . . . . . . 68 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 69 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 73 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 74 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 74 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18 contact information . . . . . . . . . . . . . . . . . . . . 75 19 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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